control_display.vhd

是一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity control_display is
    Port (clk  : in std_logic;     -- 1khz;
	       start : in std_logic;
			 cs    : out std_logic_vector(1 downto 0);
	       switch : in std_logic_vector(3 downto 0);  --数码管的显示模式,采用1～4号盘开关；
	       din1 : in std_logic_vector(15 downto 0);	  --总路程计数；
	       din2 : in std_logic_vector(15 downto 0);	  --总行车时间；
			 din3 : in std_logic_vector(15 downto 0);	  --总停车时间；
			 din4 : in std_logic_vector(15 downto 0);	  --总价格计数；
			 shift : out std_logic_vector(3 downto 0);  --数码管位选信号；
			 dout : out std_logic_vector(3 downto 0));  
end control_display;

architecture Behavioral of control_display is
type state is (st0,st1,st2,st3,st4);
signal current_state:state;

signal reg_dat : std_logic_vector(15 downto 0);
begin

process(switch,din1,din2,din3,din4)
begin
	case switch is
	when "0111" =>
	               reg_dat<=din1;
   when "1011" =>
	               reg_dat<=din2;
   when "1101" =>
	               reg_dat<=din3;
   when "1110" =>
	               reg_dat<=din4;
	when others =>
	               reg_dat<=din1;
   end case;
end process;

process(clk,start)
begin
   if start='1' then 
	             cs<="11";
	             current_state<=st4;
	             dout<="1111";
   elsif clk'event and clk='1' then	
	   case current_state is
		when st0=> 
		           cs<="10";
		           shift<="1110";
					  dout<=reg_dat(3 downto 0);
                 current_state<=st1;
      when st1=>
		           cs<="10";
		           shift<="1101";
					  dout<=reg_dat(7 downto 4);
					  current_state<=st2;
      when st2=>
		           cs<="10";
		           shift<="1011";
					  dout<=reg_dat(11 downto 8);
					  current_state<=st3;
      when st3=>
		           cs<="10";
		           shift<="0111";
					  dout<=reg_dat(15 downto 12);
					  current_state<=st0;
      when st4=>
		           cs<="00";
					  shift<="1111";
					  current_state<=st0;
		when others =>
		           null;
      end case;
   end if;
end process;
end Behavioral;