divider.vhd

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY divider IS
	PORT(iCLK:in std_logic;--input,1KHz
		oCLK:out std_logic);--output,1Hz
END divider;

ARCHITECTURE arch OF divider IS
	SIGNAL counter : integer range 0 to 499;
	SIGNAL clk_o : std_logic;
BEGIN

	prock:PROCESS(iCLK)
	begin
		if Rising_edge(iCLK) then
			if counter=499 then
				clk_o<=not clk_o;
				counter<=0;
			else
				counter<=counter+1;
			end if;
		end if;
	end process prock;

	oCLK<=clk_o;
	
END arch;