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Java书籍 Airline Reservations System A small airline has just purchased a computer for its new automated res
Airline Reservations System
A small airline has just purchased a computer for its new automated reservation system.
You have been asked to develop the new system called ARSystem. You are to write an
application to assign seats on each flight of the airline s only plane (capacity: 24 seats.)
Your app ...
汇编语言 It may analyze the window structure, the advancement and the window news, has the very greatly auxil
It may analyze the window structure, the advancement and the window news, has the very greatly auxiliary function to the development work. When we need to study some object, so long as assigns out its search window, drives the detector the indicator to assign the window/to control on to release then ...
并行计算 How the K-mean Cluster work Step 1. Begin with a decision the value of k = number of clusters S
How the K-mean Cluster work
Step 1. Begin with a decision the value of k = number of clusters
Step 2. Put any initial partition that classifies the data into k clusters. You may assign the training samples randomly, or systematically as the following:
Take the first k training sample as single-e ...
VHDL/FPGA/Verilog -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on s
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added ...
源码 The Universal Radio Hacker (URH)
The Universal Radio Hacker (URH) is a software for investigating unknown wireless protocols. Features include
* __hardware interfaces__ for common Software Defined Radios
* __easy demodulation__ of signals
* __assigning participants__ to keep overview of your data
* __customizable decodings__ to cr ...
技术资料 Verilog的135个经典设计 实例
【例3.1]4位全加器module adder 4（cout，sum i na，i nb，cin）；output[3：0]sum output cout；input[3：0]i na，i nb；input cin；assign（cout，suml=i na +i nb+ci n；endmodule【例3.2]4位计数器module count 4（out，reset，clk）；output[3：0]out；input reset，cl k；regl 3：01 out；always@posedge clk） ...
技术资料 基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明 FPGA
基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input                       clk, input                  &n ...
论文 Bi-density twin support vector machines
In this paper we present a classifier called bi-density twin support vector machines (BDTWSVMs) for data classification. In the training stage, BDTWSVMs first compute the relative density degrees for all training points using the intra-class graph whose weights are determined by a local sc ...
数据结构 表达式类型的实现: 1、 一个表达式和一颗二叉树之间
表达式类型的实现:
1、 一个表达式和一颗二叉树之间，存在着自然的对应关系。
2、 假设算术表达式Expression内可以含有变量（a～z）、常量（0～9）和二元运算符（＋，－，*，/，^）。实现一下操作。
（1） ReadExpr(E)——以字符序列的形式输入语法正确的前缀表示式并构造表达式E。
（2） WritrExpr(E)——用带括弧的中缀表 ...
书籍源码 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件
夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试）
modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk ...