搜索：VHDL - 虫虫下载站

https://www.eeworm.com/dl/663/461373.html VHDL/FPGA/Verilog

用VHDL编写的实现EDA实验中显示sin波形代码。简单易懂

用VHDL编写的实现EDA实验中显示sin波形代码。简单易懂，应该对大家都有帮助

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#VHDL #EDA #sin #编写

https://www.eeworm.com/dl/663/463753.html VHDL/FPGA/Verilog

这是一个8分频的VHDL语言设计程序

这是一个8分频的VHDL语言设计程序，也可以看成是8进制计数器

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#VHDL #分频 #语言 #设计程序

https://www.eeworm.com/dl/519/465116.html 加密解密

RC5 decryption algorithm implementation, using vhdl, with state machine implementation, use ieee pap

RC5 decryption algorithm implementation, using vhdl, with state machine implementation, use ieee papers for more detailed description.

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#implementation #decryption #algorithm #machine

https://www.eeworm.com/dl/694/466711.html 并行计算

运用VHDL语言实现四位超前进位加法器。

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#VHDL #语言 #加法器 #进位

https://www.eeworm.com/dl/663/467713.html VHDL/FPGA/Verilog

自动售货机的vhdl程序在quartus环境下编译运行通过

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#quartus #vhdl #自动售货机 #程序

https://www.eeworm.com/dl/663/468074.html VHDL/FPGA/Verilog

基于VHDL语言的一个新型串行数字通信模块。

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#VHDL #语言 #串行 #数字通信

https://www.eeworm.com/dl/663/469174.html VHDL/FPGA/Verilog

this is a very nice vhdl program for making shit and stuff... plz write back if any trouble with it.

this is a very nice vhdl program for making shit and stuff... plz write back if any trouble with it..

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#program #trouble #making #stuff

https://www.eeworm.com/dl/663/471663.html VHDL/FPGA/Verilog

RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the

RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q ...

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#using #fundamental #the #RS_latch

https://www.eeworm.com/dl/663/473074.html VHDL/FPGA/Verilog

ps2 vhdl 实现键盘输入数码管显示ascii码

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#ascii #vhdl #ps2 #键盘

https://www.eeworm.com/dl/678/473783.html 系统设计方案

能够在VHDL环境下实现密码锁的设置与开锁功能

能够在VHDL环境下实现密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动

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#VHDL #环境 #密码锁