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技术资料 FPGA的DDS实现
本文便是基于DDS(Direet Digital Synthesis)技术进行任意波形发生器研制的。要求可以产生正弦波、方波、三角波与锯齿波等常规波形，而且能够产生任意波形，从而满足研究的需要。
VHDL/FPGA/Verilog This file contains a selection of VHDL source files which serve to illustrate the diversity and powe
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp
terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. ...
VHDL/FPGA/Verilog -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com. ...
技术资料 滤波器综合手册
介绍滤波器设计的经典书籍.Handbook of Filter Synthesis, originally published in 1967 is the classic reference for continuous time filter design. The plots of filter behaviour for different designs, such as ripple and group delay, make this book invaluable. The discussion of how to synthesize a bandpa ...
系统设计方案 This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency
detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction whe ...
微处理器开发 The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and ...
其他 The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) d
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip
(SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent
method for simulation and synthesis. The library is vendor independent, with support for different
CAD tools and ta ...
笔记 Vivado时序约束
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. SDC has been in use and evolving for more than 20 years, making it the most popular and pr ...
技术资料 IEEE_Verilog_2001
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing o ...
Mentor Creating Safe State Machines(Mentor)
 
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptabl ...