搜索结果

找到约 76 项符合 ALWAYS 的查询结果
相关度 上传时间 下载量 查看数
共 76 条结果

按分类筛选

显示更多分类

书籍 RISK+COMMUNICATION

The fi rst edition of this book came about because Regina Lundgren had always been fascinated with communication. She started writing novels in the third grade. When she was asked on her fi rst day at the University of Washington what she hoped to do with her degree in scientifi c and technical comm ...
https://www.eeworm.com/dl/522101.html
下载: 1
查看: 35

书籍 SDN Software Defined Networks

The first question most readers of an O’Reilly book might ask is about the choice of the cover animal. In this case, “why a duck?” Well, for the record, our first choice was a unicorn decked out in glitter and a rainbow sash. That response always gets a laugh (we are sure you just giggled a littl ...
https://www.eeworm.com/dl/522108.html
下载: 1
查看: 45

技术资料 开关电源设计（英文版）

It all started rather innocuously. I walked into Dr GT Murthy’s office one fine day, andchanged my life. “Doc” was then the General Manager, Central R&D, of a very largeelectrical company headquartered in Bombay. In his new state-of-the-art electronics center,he had hand-picked some of India’s b ...
https://www.eeworm.com/dl/746141.html
下载: 9
查看: 9670

技术资料 FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明 使用 FPGA

FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input c ...
https://www.eeworm.com/dl/747455.html
下载: 8
查看: 1977

技术资料 基于Multisim和LabVIEW的虚实结合数字电路实验教学

实验教学一直是工科教学中不可或缺的组成部分,对培养学生的动手能力,独立思考能力,创新思维与发散思维具有重要的作用。针对目前电路教学实验中电路仿真实验与实物电路实验各自独立,无法统一问题,提出将仿真电路实验与实物电路实验有机的结合同步操作,并使用Web发布实现远程实验操作。采用Multisim作为电路实验仿真平台,NI E ...
https://www.eeworm.com/dl/832062.html
下载: 10
查看: 2792

技术资料 Verilog的135个经典设计 实例

【例3.1]4位全加器module adder 4（cout，sum i na，i nb，cin）；output[3：0]sum output cout；input[3：0]i na，i nb；input cin；assign（cout，suml=i na +i nb+ci n；endmodule【例3.2]4位计数器module count 4（out，reset，clk）；output[3：0]out；input reset，cl k；regl 3：01 out；always@posedge clk） ...
https://www.eeworm.com/dl/835557.html
下载: 8
查看: 9025