clock.fnsim.qmsg

VHDL实现的电子钟的基本功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 18 16:12:42 2009 " "Info: Processing started: Sat Apr 18 16:12:42 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter10-Behavioral " "Info: Found design unit 1: counter10-Behavioral" {  } { { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter10 " "Info: Found entity 1: counter10" {  } { { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter24-Behavioral " "Info: Found design unit 1: counter24-Behavioral" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter6-Behavioral " "Info: Found design unit 1: counter6-Behavioral" {  } { { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter6 " "Info: Found entity 1: counter6" {  } { { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-Behavioral " "Info: Found design unit 1: decoder-Behavioral" {  } { { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-Behavioral " "Info: Found design unit 1: clock-Behavioral" {  } { { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter10 counter10:u1 " "Info: Elaborating entity \"counter10\" for hierarchy \"counter10:u1\"" {  } { { "clock.vhd" "u1" { Text "E:/quretus/eleclock/clock.vhd" 60 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter6 counter6:u2 " "Info: Elaborating entity \"counter6\" for hierarchy \"counter6:u2\"" {  } { { "clock.vhd" "u2" { Text "E:/quretus/eleclock/clock.vhd" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter24 counter24:u5 " "Info: Elaborating entity \"counter24\" for hierarchy \"counter24:u5\"" {  } { { "clock.vhd" "u5" { Text "E:/quretus/eleclock/clock.vhd" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:u6 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:u6\"" {  } { { "clock.vhd" "u6" { Text "E:/quretus/eleclock/clock.vhd" 79 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "48 " "Info: Inferred 48 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux0\"" {  } { { "decoder.vhd" "Mux0" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux1\"" {  } { { "decoder.vhd" "Mux1" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux2\"" {  } { { "decoder.vhd" "Mux2" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux3\"" {  } { { "decoder.vhd" "Mux3" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux4\"" {  } { { "decoder.vhd" "Mux4" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux5\"" {  } { { "decoder.vhd" "Mux5" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u11\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u11\|Mux6\"" {  } { { "decoder.vhd" "Mux6" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux0\"" {  } { { "decoder.vhd" "Mux0" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux1\"" {  } { { "decoder.vhd" "Mux1" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux2\"" {  } { { "decoder.vhd" "Mux2" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux3\"" {  } { { "decoder.vhd" "Mux3" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux4\"" {  } { { "decoder.vhd" "Mux4" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux5\"" {  } { { "decoder.vhd" "Mux5" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u10\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u10\|Mux6\"" {  } { { "decoder.vhd" "Mux6" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux0\"" {  } { { "decoder.vhd" "Mux0" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux1\"" {  } { { "decoder.vhd" "Mux1" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux2\"" {  } { { "decoder.vhd" "Mux2" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux3\"" {  } { { "decoder.vhd" "Mux3" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux4\"" {  } { { "decoder.vhd" "Mux4" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux5\"" {  } { { "decoder.vhd" "Mux5" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u9\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u9\|Mux6\"" {  } { { "decoder.vhd" "Mux6" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux0\"" {  } { { "decoder.vhd" "Mux0" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux1\"" {  } { { "decoder.vhd" "Mux1" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux2\"" {  } { { "decoder.vhd" "Mux2" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux3\"" {  } { { "decoder.vhd" "Mux3" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux4\"" {  } { { "decoder.vhd" "Mux4" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux5\"" {  } { { "decoder.vhd" "Mux5" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u8\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u8\|Mux6\"" {  } { { "decoder.vhd" "Mux6" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux0\"" {  } { { "decoder.vhd" "Mux0" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux1\"" {  } { { "decoder.vhd" "Mux1" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux2\"" {  } { { "decoder.vhd" "Mux2" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux3\"" {  } { { "decoder.vhd" "Mux3" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux4\"" {  } { { "decoder.vhd" "Mux4" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux5\"" {  } { { "decoder.vhd" "Mux5" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u7\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u7\|Mux6\"" {  } { { "decoder.vhd" "Mux6" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux0\"" {  } { { "decoder.vhd" "Mux0" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux1\"" {  } { { "decoder.vhd" "Mux1" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux2\"" {  } { { "decoder.vhd" "Mux2" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux3\"" {  } { { "decoder.vhd" "Mux3" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux4\"" {  } { { "decoder.vhd" "Mux4" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux5\"" {  } { { "decoder.vhd" "Mux5" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "decoder:u6\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"decoder:u6\|Mux6\"" {  } { { "decoder.vhd" "Mux6" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "counter24:u5\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"counter24:u5\|Add0\"" {  } { { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "counter24:u5\|Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"counter24:u5\|Add1\"" {  } { { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add1" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "counter6:u4\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"counter6:u4\|Add0\"" {  } { { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "counter10:u3\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"counter10:u3\|Add0\"" {  } { { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "counter6:u2\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"counter6:u2\|Add0\"" {  } { { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "counter10:u1\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"counter10:u1\|Add0\"" {  } { { "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/program files/quartus/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "decoder:u11\|lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"decoder:u11\|lpm_mux:Mux0\"" {  } { { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "decoder:u11\|lpm_mux:Mux0 " "Info: Instantiated megafunction \"decoder:u11\|lpm_mux:Mux0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 16 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}