prev_cmp_clock.map.qmsg

VHDL实现的电子钟的基本功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 17 10:40:33 2009 " "Info: Processing started: Fri Apr 17 10:40:33 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT10-bhv " "Info: Found design unit 1: CNT10-bhv" {  } { { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT10 " "Info: Found entity 1: CNT10" {  } { { "counter10.vhd" "" { Text "E:/quretus/eleclock/counter10.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter24-Behavioral " "Info: Found design unit 1: counter24-Behavioral" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.vhd" "" { Text "E:/quretus/eleclock/counter24.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter6-Behavioral " "Info: Found design unit 1: counter6-Behavioral" {  } { { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter6 " "Info: Found entity 1: counter6" {  } { { "counter6.vhd" "" { Text "E:/quretus/eleclock/counter6.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-Behavioral " "Info: Found design unit 1: decoder-Behavioral" {  } { { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "E:/quretus/eleclock/decoder.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-Behavioral " "Info: Found design unit 1: clock-Behavioral" {  } { { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/quretus/eleclock/clock.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter6 counter6:u2 " "Info: Elaborating entity \"counter6\" for hierarchy \"counter6:u2\"" {  } { { "clock.vhd" "u2" { Text "E:/quretus/eleclock/clock.vhd" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter24 counter24:u5 " "Info: Elaborating entity \"counter24\" for hierarchy \"counter24:u5\"" {  } { { "clock.vhd" "u5" { Text "E:/quretus/eleclock/clock.vhd" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:u6 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:u6\"" {  } { { "clock.vhd" "u6" { Text "E:/quretus/eleclock/clock.vhd" 79 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Error" "ESGN_ENTITY_IS_MISSING" "u1 counter10 " "Error: Node instance \"u1\" instantiates undefined entity \"counter10\"" {  } { { "clock.vhd" "u1" { Text "E:/quretus/eleclock/clock.vhd" 60 0 0 } }  } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 0}
{ "Error" "ESGN_ENTITY_IS_MISSING" "u3 counter10 " "Error: Node instance \"u3\" instantiates undefined entity \"counter10\"" {  } { { "clock.vhd" "u3" { Text "E:/quretus/eleclock/clock.vhd" 68 0 0 } }  } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Error: Peak virtual memory: 172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 17 10:40:34 2009 " "Error: Processing ended: Fri Apr 17 10:40:34 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}