clock.map.summary

来自「VHDL实现的电子钟的基本功能」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Sat Apr 18 16:12:20 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Total logic elements : 75
Total pins : 64
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )