counter10.vhd.bak

VHDL实现的电子钟的基本功能

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK:IN STD_LOGIC;
     RESET:IN STD_LOGIC;
     COUNTER:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
     C:OUT STD_LOGIC);
END CNT10;
ARCHITECTURE bhv OF CNT10 IS
  SIGNAL COUNTER1:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
    COUNTER<=COUNTER1;
    PROCESS(CLK,RESET)
      BEGIN
        IF RESET='1'THEN 
           COUNTER1<="0000";
           C<='0';
        ELSIF CLK'EVENT AND CLK='1'THEN
          IF COUNTER1="1001" THEN 
             COUNTER<="0000";
             C<='0';
          ELSE 
             COUNTER1<=COUNTER1+1;
             C<='1';
          END IF;
      END IF;
    END PROCESS;
END bhv;