clock.pin

VHDL实现的电子钟的基本功能

 -- Copyright (C) 1991-2008 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
 -- (including device programming or simulation files), and any 
 -- associated documentation or information are expressly subject 
 -- to the terms and conditions of the Altera Program License 
 -- Subscription Agreement, Altera MegaCore Function License 
 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
 -- programming logic devices manufactured by Altera and sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
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 -- NC            : No Connect. This pin has no internal connection to the device.
 -- DNU           : Do Not Use. This pin MUST NOT be connected.
 -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.8V).
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 --					Bank 1:		3.3V
 --					Bank 2:		3.3V
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin.   For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
 --           	    connect each pin marked GND* either individually through a 10 kohm resistor
 --           	    to GND or tie all pins together and connect through a single 10 kohm resistor
 --           	    to GND.
 --           	    For non-transceiver I/O banks, connect each pin marked GND* directly to GND
 --           	    or leave it unconnected.
 -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
 -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
 -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
 -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
 -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
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 -- Pin directions (input, output or bidir) are based on device operating in user mode.
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Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version
CHIP  "clock"  ASSIGNED TO AN: EPM570ZM100C7

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
secondl[1]                   : A1        : output : 3.3-V LVTTL       :         : 2         : N              
minuteh[0]                   : A2        : output : 3.3-V LVTTL       :         : 2         : N              
minuteh[1]                   : A3        : output : 3.3-V LVTTL       :         : 2         : N              
GND*                         : A4        :        :                   :         : 2         :                
hourh[5]                     : A5        : output : 3.3-V LVTTL       :         : 2         : N              
secondl[3]                   : A6        : output : 3.3-V LVTTL       :         : 2         : N              
dinh[3]                      : A7        : input  : 3.3-V LVTTL       :         : 2         : N              
secondl[4]                   : A8        : output : 3.3-V LVTTL       :         : 2         : N              
minutel[3]                   : A9        : output : 3.3-V LVTTL       :         : 2         : N              
dinm[5]                      : A10       : input  : 3.3-V LVTTL       :         : 2         : N              
dinh[2]                      : A11       : input  : 3.3-V LVTTL       :         : 2         : N              
GND*                         : B1        :        :                   :         : 1         :                
secondl[5]                   : B2        : output : 3.3-V LVTTL       :         : 2         : N              
secondh[4]                   : B3        : output : 3.3-V LVTTL       :         : 2         : N              
hourl[6]                     : B4        : output : 3.3-V LVTTL       :         : 2         : N              
hourl[3]                     : B5        : output : 3.3-V LVTTL       :         : 2         : N              
secondh[1]                   : B6        : output : 3.3-V LVTTL       :         : 2         : N