clock.fit.summary

来自「VHDL实现的电子钟的基本功能」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Sat Apr 18 16:12:26 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Device : EPM570ZM100C7
Timing Models : Preliminary
Total logic elements : 67 / 570 ( 12 % )
Total pins : 64 / 76 ( 84 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )