clock.tan.rpt

VHDL实现的电子钟的基本功能

; N/A   ; None         ; 30.523 ns  ; counter10:u3|count[1] ; minutel[4] ; clk        ;
; N/A   ; None         ; 30.156 ns  ; counter10:u3|count[3] ; minutel[0] ; clk        ;
; N/A   ; None         ; 30.051 ns  ; counter10:u3|count[0] ; minutel[3] ; clk        ;
; N/A   ; None         ; 29.996 ns  ; counter10:u3|count[0] ; minutel[4] ; clk        ;
; N/A   ; None         ; 29.575 ns  ; counter10:u3|count[0] ; minutel[0] ; clk        ;
; N/A   ; None         ; 28.498 ns  ; counter6:u2|count[1]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 27.500 ns  ; counter6:u2|count[2]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 27.056 ns  ; counter6:u2|count[0]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 25.808 ns  ; counter6:u2|count[1]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 25.302 ns  ; counter6:u2|count[2]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 25.148 ns  ; counter6:u2|count[1]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 25.148 ns  ; counter6:u2|count[1]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 25.087 ns  ; counter6:u2|count[1]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 24.643 ns  ; counter6:u2|count[2]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 24.642 ns  ; counter6:u2|count[2]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 24.582 ns  ; counter6:u2|count[2]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 24.366 ns  ; counter6:u2|count[0]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 24.163 ns  ; counter6:u2|count[1]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 23.706 ns  ; counter6:u2|count[0]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 23.703 ns  ; counter6:u2|count[0]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 23.645 ns  ; counter6:u2|count[0]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 23.291 ns  ; counter6:u2|count[2]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 22.962 ns  ; counter6:u2|count[1]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 22.733 ns  ; counter6:u2|count[0]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 22.090 ns  ; counter6:u2|count[2]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 21.533 ns  ; counter6:u2|count[0]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 18.909 ns  ; counter10:u1|count[1] ; secondl[6] ; clk        ;
; N/A   ; None         ; 18.350 ns  ; counter10:u1|count[3] ; secondl[5] ; clk        ;
; N/A   ; None         ; 17.532 ns  ; counter10:u1|count[1] ; secondl[1] ; clk        ;
; N/A   ; None         ; 17.373 ns  ; counter10:u1|count[2] ; secondl[1] ; clk        ;
; N/A   ; None         ; 16.871 ns  ; counter10:u1|count[2] ; secondl[6] ; clk        ;
; N/A   ; None         ; 16.862 ns  ; counter10:u1|count[3] ; secondl[4] ; clk        ;
; N/A   ; None         ; 16.836 ns  ; counter10:u1|count[3] ; secondl[3] ; clk        ;
; N/A   ; None         ; 16.790 ns  ; counter10:u1|count[2] ; secondl[5] ; clk        ;
; N/A   ; None         ; 16.547 ns  ; counter10:u1|count[1] ; secondl[0] ; clk        ;
; N/A   ; None         ; 16.419 ns  ; counter10:u1|count[3] ; secondl[1] ; clk        ;
; N/A   ; None         ; 16.389 ns  ; counter10:u1|count[2] ; secondl[0] ; clk        ;
; N/A   ; None         ; 16.017 ns  ; counter10:u1|count[0] ; secondl[6] ; clk        ;
; N/A   ; None         ; 15.922 ns  ; counter10:u1|count[0] ; secondl[5] ; clk        ;
; N/A   ; None         ; 15.891 ns  ; counter10:u1|count[0] ; secondl[1] ; clk        ;
; N/A   ; None         ; 15.715 ns  ; counter10:u1|count[3] ; secondl[2] ; clk        ;
; N/A   ; None         ; 15.588 ns  ; counter10:u1|count[0] ; secondl[2] ; clk        ;
; N/A   ; None         ; 15.434 ns  ; counter10:u1|count[3] ; secondl[0] ; clk        ;
; N/A   ; None         ; 15.306 ns  ; counter10:u1|count[0] ; secondl[4] ; clk        ;
; N/A   ; None         ; 15.272 ns  ; counter10:u1|count[0] ; secondl[3] ; clk        ;
; N/A   ; None         ; 15.252 ns  ; counter10:u1|count[3] ; secondl[6] ; clk        ;
; N/A   ; None         ; 15.158 ns  ; counter10:u1|count[1] ; secondl[5] ; clk        ;
; N/A   ; None         ; 14.903 ns  ; counter10:u1|count[0] ; secondl[0] ; clk        ;
; N/A   ; None         ; 14.627 ns  ; counter10:u1|count[1] ; secondl[2] ; clk        ;
; N/A   ; None         ; 14.434 ns  ; counter10:u1|count[2] ; secondl[4] ; clk        ;
; N/A   ; None         ; 14.413 ns  ; counter10:u1|count[2] ; secondl[3] ; clk        ;
; N/A   ; None         ; 14.073 ns  ; counter10:u1|count[2] ; secondl[2] ; clk        ;
; N/A   ; None         ; 13.657 ns  ; counter10:u1|count[1] ; secondl[4] ; clk        ;
; N/A   ; None         ; 13.644 ns  ; counter10:u1|count[1] ; secondl[3] ; clk        ;
+-------+--------------+------------+-----------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Sat Apr 18 16:12:30 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Warning: Timing characteristics of device EPM570ZM100C7 are preliminary
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter6:u4|c" as buffer
    Info: Detected ripple clock "counter10:u3|c" as buffer
    Info: Detected ripple clock "counter6:u2|c" as buffer
    Info: Detected ripple clock "counter10:u1|c" as buffer
Info: Clock "clk" has Internal fmax of 78.97 MHz between source register "counter24:u5|count[0]" and destination register "counter24:u5|count[5]" (period= 12.663 ns)
    Info: + Longest register to register delay is 11.855 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N0; Fanout = 13; REG Node = 'counter24:u5|count[0]'
        Info: 2: + IC(4.206 ns) + CELL(2.247 ns) = 6.453 ns; Loc. = LC_X8_Y6_N6; Fanout = 2; COMB Node = 'counter24:u5|Equal1~36'
        Info: 3: + IC(2.477 ns) + CELL(2.925 ns) = 11.855 ns; Loc. = LC_X7_Y6_N3; Fanout = 6; REG Node = 'counter24:u5|count[5]'
        Info: Total cell delay = 5.172 ns ( 43.63 % )
        Info: Total interconnect delay = 6.683 ns ( 56.37 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 34.345 ns
            Info: 1: + IC(0.000 ns) + CELL(0.970 ns) = 0.970 ns; Loc. = PIN_F2; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.590 ns) + CELL(2.113 ns) = 4.673 ns; Loc. = LC_X8_Y4_N9; Fanout = 4; REG Node = 'counter10:u1|c'
            Info: 3: + IC(6.641 ns) + CELL(2.113 ns) = 13.427 ns; Loc. = LC_X11_Y4_N9; Fanout = 5; REG Node = 'counter6:u2|c'
            Info: 4: + IC(6.010 ns) + CELL(2.113 ns) = 21.550 ns; Loc. = LC_X10_Y6_N9; Fanout = 4; REG Node = 'counter10:u3|c'
            Info: 5: + IC(4.286 ns) + CELL(2.113 ns) = 27.949 ns; Loc. = LC_X9_Y4_N7; Fanout = 6; REG Node = 'counter6:u4|c'
            Info: 6: + IC(4.772 ns) + CELL(1.624 ns) = 34.345 ns; Loc. = LC_X7_Y6_N3; Fanout = 6; REG Node = 'counter24:u5|count[5]'
            Info: Total cell delay = 11.046 ns ( 32.16 % )
            Info: Total interconnect delay = 23.299 ns ( 67.84 % )
        Info: - Longest clock path from clock "clk" to source register is 34.345 ns
            Info: 1: + IC(0.000 ns) + CELL(0.970 ns) = 0.970 ns; Loc. = PIN_F2; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.590 ns) + CELL(2.113 ns) = 4.673 ns; Loc. = LC_X8_Y4_N9; Fanout = 4; REG Node = 'counter10:u1|c'
            Info: 3: + IC(6.641 ns) + CELL(2.113 ns) = 13.427 ns; Loc. = LC_X11_Y4_N9; Fanout = 5; REG Node = 'counter6:u2|c'
            Info: 4: + IC(6.010 ns) + CELL(2.113 ns) = 21.550 ns; Loc. = LC_X10_Y6_N9; Fanout = 4; REG Node = 'counter10:u3|c'
            Info: 5: + IC(4.286 ns) + CELL(2.113 ns) = 27.949 ns; Loc. = LC_X9_Y4_N7; Fanout = 6; REG Node = 'counter6:u4|c'
            Info: 6: + IC(4.772 ns) + CELL(1.624 ns) = 34.345 ns; Loc. = LC_X8_Y6_N0; Fanout = 13; REG Node = 'counter24:u5|count[0]'
            Info: Total cell delay = 11.046 ns ( 32.16 % )
            Info: Total interconnect delay = 23.299 ns ( 67.84 % )
    Info: + Micro clock to output delay of source is 0.489 ns
    Info: + Micro setup delay of destination is 0.319 ns
Info: tco from clock "clk" to destination pin "hourh[2]" through register "counter24:u5|count[2]" is 47.520 ns
    Info: + Longest clock path from clock "clk" to source register is 34.345 ns
        Info: 1: + IC(0.000 ns) + CELL(0.970 ns) = 0.970 ns; Loc. = PIN_F2; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.590 ns) + CELL(2.113 ns) = 4.673 ns; Loc. = LC_X8_Y4_N9; Fanout = 4; REG Node = 'counter10:u1|c'
        Info: 3: + IC(6.641 ns) + CELL(2.113 ns) = 13.427 ns; Loc. = LC_X11_Y4_N9; Fanout = 5; REG Node = 'counter6:u2|c'
        Info: 4: + IC(6.010 ns) + CELL(2.113 ns) = 21.550 ns; Loc. = LC_X10_Y6_N9; Fanout = 4; REG Node = 'counter10:u3|c'
        Info: 5: + IC(4.286 ns) + CELL(2.113 ns) = 27.949 ns; Loc. = LC_X9_Y4_N7; Fanout = 6; REG Node = 'counter6:u4|c'
        Info: 6: + IC(4.772 ns) + CELL(1.624 ns) = 34.345 ns; Loc. = LC_X7_Y6_N6; Fanout = 12; REG Node = 'counter24:u5|count[2]'
        Info: Total cell delay = 11.046 ns ( 32.16 % )
        Info: Total interconnect delay = 23.299 ns ( 67.84 % )
    Info: + Micro clock to output delay of source is 0.489 ns
    Info: + Longest register to pin delay is 12.686 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N6; Fanout = 12; REG Node = 'counter24:u5|count[2]'
        Info: 2: + IC(3.169 ns) + CELL(0.968 ns) = 4.137 ns; Loc. = LC_X8_Y6_N1; Fanout = 1; COMB Node = 'decoder:u10|Mux4~29'
        Info: 3: + IC(6.575 ns) + CELL(1.974 ns) = 12.686 ns; Loc. = PIN_D1; Fanout = 0; PIN Node = 'hourh[2]'
        Info: Total cell delay = 2.942 ns ( 23.19 % )
        Info: Total interconnect delay = 9.744 ns ( 76.81 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Sat Apr 18 16:12:31 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01