📄 clock.tan.rpt
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Classic Timing Analyzer report for clock
Sat Apr 18 16:12:31 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 47.520 ns ; counter24:u5|count[2] ; hourh[2] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 78.97 MHz ( period = 12.663 ns ) ; counter24:u5|count[0] ; counter24:u5|count[5] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM570ZM100C7 ; ; ; ;
; Timing Models ; Preliminary ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 78.97 MHz ( period = 12.663 ns ) ; counter24:u5|count[0] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 11.855 ns ;
; N/A ; 79.01 MHz ( period = 12.656 ns ) ; counter24:u5|count[0] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 11.848 ns ;
; N/A ; 86.42 MHz ( period = 11.571 ns ) ; counter24:u5|count[3] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 10.763 ns ;
; N/A ; 87.38 MHz ( period = 11.444 ns ) ; counter24:u5|count[4] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 10.636 ns ;
; N/A ; 87.44 MHz ( period = 11.437 ns ) ; counter24:u5|count[4] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 10.629 ns ;
; N/A ; 89.17 MHz ( period = 11.215 ns ) ; counter24:u5|count[2] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 10.407 ns ;
; N/A ; 89.22 MHz ( period = 11.208 ns ) ; counter24:u5|count[2] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 10.400 ns ;
; N/A ; 91.93 MHz ( period = 10.878 ns ) ; counter24:u5|count[1] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 10.070 ns ;
; N/A ; 92.54 MHz ( period = 10.806 ns ) ; counter24:u5|count[5] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 9.998 ns ;
; N/A ; 92.60 MHz ( period = 10.799 ns ) ; counter24:u5|count[5] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 9.991 ns ;
; N/A ; 94.25 MHz ( period = 10.610 ns ) ; counter24:u5|count[1] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 9.802 ns ;
; N/A ; 103.14 MHz ( period = 9.696 ns ) ; counter24:u5|count[3] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 8.888 ns ;
; N/A ; 117.19 MHz ( period = 8.533 ns ) ; counter24:u5|count[1] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 7.725 ns ;
; N/A ; 119.08 MHz ( period = 8.398 ns ) ; counter10:u1|count[1] ; counter10:u1|c ; clk ; clk ; None ; None ; 7.590 ns ;
; N/A ; 123.27 MHz ( period = 8.112 ns ) ; counter24:u5|count[0] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 7.304 ns ;
; N/A ; 124.55 MHz ( period = 8.029 ns ) ; counter24:u5|count[2] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 7.221 ns ;
; N/A ; 125.55 MHz ( period = 7.965 ns ) ; counter24:u5|count[1] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 7.157 ns ;
; N/A ; 126.01 MHz ( period = 7.936 ns ) ; counter24:u5|count[0] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 7.128 ns ;
; N/A ; 129.00 MHz ( period = 7.752 ns ) ; counter6:u2|count[1] ; counter6:u2|c ; clk ; clk ; None ; None ; 6.944 ns ;
; N/A ; 129.10 MHz ( period = 7.746 ns ) ; counter10:u3|count[2] ; counter10:u3|count[1] ; clk ; clk ; None ; None ; 6.938 ns ;
; N/A ; 129.43 MHz ( period = 7.726 ns ) ; counter24:u5|count[0] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 6.918 ns ;
; N/A ; 132.40 MHz ( period = 7.553 ns ) ; counter24:u5|count[2] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 6.745 ns ;
; N/A ; 144.22 MHz ( period = 6.934 ns ) ; counter24:u5|count[3] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 6.126 ns ;
; N/A ; 155.67 MHz ( period = 6.424 ns ) ; counter10:u3|count[2] ; counter10:u3|c ; clk ; clk ; None ; None ; 5.616 ns ;
; N/A ; 156.81 MHz ( period = 6.377 ns ) ; counter24:u5|count[2] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 5.569 ns ;
; N/A ; 157.06 MHz ( period = 6.367 ns ) ; counter10:u1|count[2] ; counter10:u1|c ; clk ; clk ; None ; None ; 5.559 ns ;
; N/A ; 162.07 MHz ( period = 6.170 ns ) ; counter10:u3|count[1] ; counter10:u3|c ; clk ; clk ; None ; None ; 5.362 ns ;
; N/A ; 163.69 MHz ( period = 6.109 ns ) ; counter6:u4|count[1] ; counter6:u4|count[2] ; clk ; clk ; None ; None ; 5.301 ns ;
; N/A ; 163.85 MHz ( period = 6.103 ns ) ; counter6:u2|count[2] ; counter6:u2|c ; clk ; clk ; None ; None ; 5.295 ns ;
; N/A ; 164.47 MHz ( period = 6.080 ns ) ; counter6:u4|count[1] ; counter6:u4|c ; clk ; clk ; None ; None ; 7.827 ns ;
; N/A ; 168.86 MHz ( period = 5.922 ns ) ; counter6:u2|count[0] ; counter6:u2|c ; clk ; clk ; None ; None ; 5.114 ns ;
; N/A ; 176.96 MHz ( period = 5.651 ns ) ; counter6:u4|count[0] ; counter6:u4|count[1] ; clk ; clk ; None ; None ; 4.843 ns ;
; N/A ; 177.12 MHz ( period = 5.646 ns ) ; counter6:u4|count[0] ; counter6:u4|count[2] ; clk ; clk ; None ; None ; 4.838 ns ;
; N/A ; 177.90 MHz ( period = 5.621 ns ) ; counter10:u3|count[1] ; counter10:u3|count[3] ; clk ; clk ; None ; None ; 4.813 ns ;
; N/A ; 178.00 MHz ( period = 5.618 ns ) ; counter10:u3|count[1] ; counter10:u3|count[2] ; clk ; clk ; None ; None ; 4.810 ns ;
; N/A ; 178.54 MHz ( period = 5.601 ns ) ; counter10:u1|count[1] ; counter10:u1|count[3] ; clk ; clk ; None ; None ; 4.793 ns ;
; N/A ; 178.64 MHz ( period = 5.598 ns ) ; counter10:u1|count[1] ; counter10:u1|count[2] ; clk ; clk ; None ; None ; 4.790 ns ;
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