clock.sdc

VHDL实现的电子钟的基本功能

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# Generated by : Version 8.1 Build 163 10/28/2008 SJ Full Version
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# Project      : clock
# Revision     : clock
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# Date         : Sat Apr 18 16:20:30 中国标准时间 2009
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# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
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# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
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# ** Clock Latency
#    -------------

# ** Clock Uncertainty
#    -----------------

# ** Multicycles
#    -----------
# ** Cuts
#    ----

# ** Input/Output Delays
#    -------------------




# ** Tpd requirements
#    ----------------

# ** Setup/Hold Relationships
#    ------------------------

# ** Tsu/Th requirements
#    -------------------


# ** Tco/MinTco requirements
#    -----------------------

#
# Entity Specific Timing Assignments found in
# the Timing Analyzer Settings report panel
#


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