uart_txd.flow.rpt

基于verilog hdl的UART串口发送子程序。

Flow report for uart_txd
Mon May 11 14:39:45 2009
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Flow Summary                                                                  ;
+------------------------------------+------------------------------------------+
; Flow Status                        ; Successful - Mon May 11 14:39:44 2009    ;
; Quartus II Version                 ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name                      ; uart_txd                                 ;
; Top-level Entity Name              ; uart_txd                                 ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C5T144C8                              ;
; Timing Models                      ; Final                                    ;
; Met timing requirements            ; Yes                                      ;
; Total logic elements               ; 0 / 4,608 ( 0 % )                        ;
;     Total combinational functions  ; 0 / 4,608 ( 0 % )                        ;
;     Dedicated logic registers      ; 0 / 4,608 ( 0 % )                        ;
; Total registers                    ; 0                                        ;
; Total pins                         ; 13 / 89 ( 15 % )                         ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0 / 119,808 ( 0 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                           ;
; Total PLLs                         ; 0 / 2 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 05/11/2009 14:39:14 ;
; Main task         ; Compilation         ;
; Revision Name     ; uart_txd            ;
+-------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                  ;
+------------------------------------+-------------------------------+---------------+-------------+----------------+
; Assignment Name                    ; Value                         ; Default Value ; Entity Name ; Section Id     ;
+------------------------------------+-------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID              ; 1096087392084.124202395305488 ; --            ; --          ; --             ;
; MAX_CORE_JUNCTION_TEMP             ; 85                            ; --            ; --          ; --             ;
; MIN_CORE_JUNCTION_TEMP             ; 0                             ; --            ; --          ; --             ;
; PARTITION_COLOR                    ; 16764057                      ; --            ; --          ; Top            ;
; PARTITION_NETLIST_TYPE             ; SOURCE                        ; --            ; --          ; Top            ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                           ; --            ; --          ; eda_blast_fpga ;
+------------------------------------+-------------------------------+---------------+-------------+----------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ; 168 MB              ; 00:00:02                           ;
; Fitter                  ; 00:00:06     ; 1.0                     ; 183 MB              ; 00:00:04                           ;
; Assembler               ; 00:00:07     ; 1.0                     ; 156 MB              ; 00:00:05                           ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ; 121 MB              ; 00:00:01                           ;
; Total                   ; 00:00:16     ; --                      ; --                  ; 00:00:12                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


+---------------------------------------------------------------------------------------+
; Flow OS Summary                                                                       ;
+-------------------------+------------------+------------+------------+----------------+
; Module Name             ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
+-------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis    ; zhoudaxian       ; Windows XP ; 5.1        ; i686           ;
; Fitter                  ; zhoudaxian       ; Windows XP ; 5.1        ; i686           ;
; Assembler               ; zhoudaxian       ; Windows XP ; 5.1        ; i686           ;
; Classic Timing Analyzer ; zhoudaxian       ; Windows XP ; 5.1        ; i686           ;
+-------------------------+------------------+------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off uart_txd -c uart_txd
quartus_fit --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd
quartus_asm --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd
quartus_tan --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd --timing_analysis_only