uart_txd.qsf

基于verilog hdl的UART串口发送子程序。

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# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
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# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# applicable agreement for further details.
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#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Full Version
# Date created = 21:19:32  May 10, 2009
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		uart_txd_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5T144C8
set_global_assignment -name TOP_LEVEL_ENTITY uart_txd
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:19:32  MAY 10, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name SOURCE_FILE uart_txd
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VERILOG_FILE uart_txd.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VECTOR_WAVEFORM_FILE uart_txd.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE uart_txd.vwf