uart_txd.v

基于verilog hdl的UART串口发送子程序。

/******************************************************************************
*
*    File Name:  uart_txd.v
*      Version:  1.1
*         Date:  May 04, 2009
*        Model:  Uart Chip
*      Company:  XiHua
* 
******************************************************************************/
module uart_txd(clk_in,
				clk_out,
				data_in,
				TXD,
				TI,
				txd_en
				);
	input 		clk_in;//clock input
	input		txd_en;//send data enable
	input		[7:0]data_in;//data for send
	output		clk_out;//clock output (baud rate)
	output		TXD;//send 1bit
	output      TI;//send intrrupt flag 
	
	reg			[9:0]buffer;//data buffer
	reg			[9:0]buffer_reg;//data buffer reg
	reg			start_flag;//start flag
	reg			[12:0]count_baud;//frequency counter
	reg			[3:0]count_bit;//bit counter
	reg			TI;//send intrrupt flag 
	reg			txd_reg;//send 1bit reg
	reg 		clk_baud;//Baud rate frequency
	
	parameter	frequency=20_000_000,//20MHZ clock
	            baud_rate=9600,//Baud rate is 9600
				sub_freq=(1/baud_rate)/(1/frequency);//Sub-frequency
													 //1_0100_0101_1000	
	assign		TXD=txd_reg;//data sendout
	assign		clk_out=clk_baud;//clock output
	//Baud rate frequency
	//
	always @(posedge clk_in)
		begin
			if(count_baud==sub_freq)//count overfull
				count_baud <= 12'h0;
			else
				count_baud <= count_baud +12'h1;
		end			
	always @(negedge clk_in)
		begin
			if(count_baud==sub_freq)
				clk_baud <= !clk_baud;
		end
	//read data to buffer
	always @(posedge clk_in)
		begin
			if(txd_en)
				begin
					buffer[9:0]={1'b1,data_in[7:0],1'b0};//10 bit :start and end flag bit and 8bit data
					start_flag= 1'b1;//start flag 
				end
			else if(TI==0)//
				start_flag=1'b0;
		end
	//send data out per 1 bit
	always @(posedge clk_in)
		begin
			if(clk_baud)
				begin
					if(start_flag==1||count_bit<4'd10)//
						begin
							if(count_bit<4'd10)
								begin
									txd_reg=buffer_reg[0];//start bit
									buffer_reg=buffer>>count_bit;//trans
									count_bit=count_bit+4'd1;
									TI=1'b0;
								end
							else
								count_bit=4'b0;//send over 1 byte
						end
					else//idel or finish send data,TXD and TI hold high
						begin
							txd_reg=1'b1;
							TI=1'b1;
						end
				end
		end
endmodule