uart_txd.vt

基于verilog hdl的UART串口发送子程序。

// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "05/11/2009 14:32:37"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    uart_txd
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module uart_txd_vlg_sample_tst(
	clk_in,
	data_in,
	txd_en,
	sampler_tx
);
input  clk_in;
input [7:0] data_in;
input  txd_en;
output sampler_tx;

reg sample;
time current_time;
always @(clk_in or data_in or txd_en)
                                                                                
begin                                         
 if ($time > 0)                               
 begin                                        
	if ($time == 0 || $time != current_time)  
	begin									  
		if (sample === 1'bx)                  
			sample = 0;                       
		else                                  
			sample = ~sample;                 
	end										  
	current_time = $time;					  
 end                                          
end                                           

assign sampler_tx = sample;
endmodule

module uart_txd_vlg_check_tst (
	TI,TXD,clk_out,sampler_rx
);
input  TI;
input  TXD;
input  clk_out;
input sampler_rx;

reg  TI_expected;
reg  TXD_expected;
reg  clk_out_expected;

reg  TI_prev;
reg  TXD_prev;
reg  clk_out_prev;

reg  TI_expected_prev;
reg  TXD_expected_prev;
reg  clk_out_expected_prev;

reg  last_TI_exp;
reg  last_TXD_exp;
reg  last_clk_out_exp;

reg trigger;

integer i;
integer nummismatches;

reg [1:3] on_first_change ;


initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 3'b1;
end

// update real /o prevs

always @(trigger)
begin
	TI_prev = TI;
	TXD_prev = TXD;
	clk_out_prev = clk_out;
end

// update expected /o prevs

always @(trigger)
begin
	TI_expected_prev = TI_expected;
	TXD_expected_prev = TXD_expected;
	clk_out_expected_prev = clk_out_expected;
end



// expected TI
initial
begin
	TI_expected = 1'bX;
end 

// expected TXD
initial
begin
	TXD_expected = 1'bX;
end 

// expected clk_out
initial
begin
	clk_out_expected = 1'bX;
end 
// generate trigger
always @(TI_expected or TI or TXD_expected or TXD or clk_out_expected or clk_out)
begin
	trigger <= ~trigger;
end

always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
	$display("Scanning pattern %d @time = %t",i,$realtime );
	i = i + 1;
	$display("| expected TI = %b | expected TXD = %b | expected clk_out = %b | ",TI_expected_prev,TXD_expected_prev,clk_out_expected_prev);
	$display("| real TI = %b | real TXD = %b | real clk_out = %b | ",TI_prev,TXD_prev,clk_out_prev);
`endif
	if (
		( TI_expected_prev !== 1'bx ) && ( TI_prev !== TI_expected_prev )
		&& ((TI_expected_prev !== last_TI_exp) ||
			on_first_change[1])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port TI :: @time = %t",  $realtime);
		$display ("     Expected value = %b", TI_expected_prev);
		$display ("     Real value = %b", TI_prev);
		nummismatches = nummismatches + 1;
		on_first_change[1] = 1'b0;
		last_TI_exp = TI_expected_prev;
	end
	if (
		( TXD_expected_prev !== 1'bx ) && ( TXD_prev !== TXD_expected_prev )
		&& ((TXD_expected_prev !== last_TXD_exp) ||
			on_first_change[2])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port TXD :: @time = %t",  $realtime);
		$display ("     Expected value = %b", TXD_expected_prev);
		$display ("     Real value = %b", TXD_prev);
		nummismatches = nummismatches + 1;
		on_first_change[2] = 1'b0;
		last_TXD_exp = TXD_expected_prev;
	end
	if (
		( clk_out_expected_prev !== 1'bx ) && ( clk_out_prev !== clk_out_expected_prev )
		&& ((clk_out_expected_prev !== last_clk_out_exp) ||
			on_first_change[3])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port clk_out :: @time = %t",  $realtime);
		$display ("     Expected value = %b", clk_out_expected_prev);
		$display ("     Real value = %b", clk_out_prev);
		nummismatches = nummismatches + 1;
		on_first_change[3] = 1'b0;
		last_clk_out_exp = clk_out_expected_prev;
	end

	trigger <= ~trigger;
end
initial 

begin 
$timeformat(-12,3," ps",6);
#1000000;
if (nummismatches > 0)
	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
	$display ("Simulation passed !");
$stop;
end 
endmodule

module uart_txd_vlg_vec_tst();
// constants                                           
// general purpose registers
reg clk_in;
reg [7:0] data_in;
reg txd_en;
// wires                                               
wire TI;
wire TXD;
wire clk_out;

wire sampler;                             

// assign statements (if any)                          
uart_txd i1 (
// port map - connection between master ports and signals/registers   
	.TI(TI),
	.TXD(TXD),
	.clk_in(clk_in),
	.clk_out(clk_out),
	.data_in(data_in),
	.txd_en(txd_en)
);

// txd_en
initial
begin
	txd_en = 1'b0;
end 

// clk_in
initial
begin
	clk_in = 1'b0;
end 
// data_in[ 7 ]
initial
begin
	data_in[7] = 1'b0;
end 
// data_in[ 6 ]
initial
begin
	data_in[6] = 1'b0;
end 
// data_in[ 5 ]
initial
begin
	data_in[5] = 1'b0;
end 
// data_in[ 4 ]
initial
begin
	data_in[4] = 1'b0;
end 
// data_in[ 3 ]
initial
begin
	data_in[3] = 1'b0;
end 
// data_in[ 2 ]
initial
begin
	data_in[2] = 1'b0;
end 
// data_in[ 1 ]
initial
begin
	data_in[1] = 1'b0;
end 
// data_in[ 0 ]
initial
begin
	data_in[0] = 1'b0;
end 

uart_txd_vlg_sample_tst tb_sample (
	.clk_in(clk_in),
	.data_in(data_in),
	.txd_en(txd_en),
	.sampler_tx(sampler)
);

uart_txd_vlg_check_tst tb_out(
	.TI(TI),
	.TXD(TXD),
	.clk_out(clk_out),
	.sampler_rx(sampler)
);
endmodule