uart_txd.fit.summary

基于verilog hdl的UART串口发送子程序。

Fitter Status : Successful - Mon May 11 14:39:26 2009
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
Revision Name : uart_txd
Top-level Entity Name : uart_txd
Family : Cyclone II
Device : EP2C5T144C8
Timing Models : Final
Total logic elements : 0 / 4,608 ( 0 % )
    Total combinational functions : 0 / 4,608 ( 0 % )
    Dedicated logic registers : 0 / 4,608 ( 0 % )
Total registers : 0
Total pins : 13 / 89 ( 15 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )