uart_txd.map.summary

基于verilog hdl的UART串口发送子程序。

Analysis & Synthesis Status : Successful - Mon May 11 14:39:16 2009
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
Revision Name : uart_txd
Top-level Entity Name : uart_txd
Family : Cyclone II
Total logic elements : 0
    Total combinational functions : 0
    Dedicated logic registers : 0
Total registers : 0
Total pins : 13
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0