cnt10.tan.qmsg

带复位和时钟使能的十进制计数器 verilo 描述

{ "Info" "ITDB_FULL_TCO_RESULT" "clk led7s\[4\] cqi\[0\] 14.581 ns register " "Info: tco from clock \"clk\" to destination pin \"led7s\[4\]\" through register \"cqi\[0\]\" is 14.581 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.109 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J16 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.711 ns) 3.109 ns cqi\[0\] 2 REG LC_X6_Y13_N2 13 " "Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi\[0\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.640 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.12 % " "Info: Total cell delay = 2.180 ns ( 70.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.929 ns 29.88 % " "Info: Total interconnect delay = 0.929 ns ( 29.88 % )" {  } {  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[0] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.248 ns + Longest register pin " "Info: + Longest register to pin delay is 11.248 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cqi\[0\] 1 REG LC_X6_Y13_N2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi\[0\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cqi[0] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.590 ns) 1.314 ns Mux~302 2 COMB LC_X6_Y13_N6 14 " "Info: 2: + IC(0.724 ns) + CELL(0.590 ns) = 1.314 ns; Loc. = LC_X6_Y13_N6; Fanout = 14; COMB Node = 'Mux~302'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.314 ns" { cqi[0] Mux~302 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.046 ns) 6.360 ns led7s\[4\]\$latch 3 COMB LOOP LC_X5_Y13_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(5.046 ns) = 6.360 ns; Loc. = LC_X5_Y13_N4; Fanout = 2; COMB LOOP Node = 'led7s\[4\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "led7s\[4\]\$latch LC_X5_Y13_N4 " "Info: Loc. = LC_X5_Y13_N4; Node \"led7s\[4\]\$latch\"" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { led7s[4]$latch } "NODE_NAME" } "" } }  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { led7s[4]$latch } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "5.046 ns" { Mux~302 led7s[4]$latch } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.764 ns) + CELL(2.124 ns) 11.248 ns led7s\[4\] 4 PIN PIN_H1 0 " "Info: 4: + IC(2.764 ns) + CELL(2.124 ns) = 11.248 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'led7s\[4\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "4.888 ns" { led7s[4]$latch led7s[4] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.760 ns 68.99 % " "Info: Total cell delay = 7.760 ns ( 68.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.488 ns 31.01 % " "Info: Total interconnect delay = 3.488 ns ( 31.01 % )" {  } {  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "11.248 ns" { cqi[0] Mux~302 led7s[4]$latch led7s[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.248 ns" { cqi[0] Mux~302 led7s[4]$latch led7s[4] } { 0.000ns 0.724ns 0.000ns 2.764ns } { 0.000ns 0.590ns 5.046ns 2.124ns } } }  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[0] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "11.248 ns" { cqi[0] Mux~302 led7s[4]$latch led7s[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.248 ns" { cqi[0] Mux~302 led7s[4]$latch led7s[4] } { 0.000ns 0.724ns 0.000ns 2.764ns } { 0.000ns 0.590ns 5.046ns 2.124ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[1\] led_selout\[3\] 19.090 ns Longest " "Info: Longest tpd from source pin \"b\[1\]\" to destination pin \"led_selout\[3\]\" is 19.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns b\[1\] 1 PIN PIN_N14 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_N14; Fanout = 8; PIN Node = 'b\[1\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { b[1] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(13.375 ns) + CELL(0.590 ns) 15.434 ns Mux~296 2 COMB LC_X1_Y26_N2 1 " "Info: 2: + IC(13.375 ns) + CELL(0.590 ns) = 15.434 ns; Loc. = LC_X1_Y26_N2; Fanout = 1; COMB Node = 'Mux~296'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "13.965 ns" { b[1] Mux~296 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.532 ns) + CELL(2.124 ns) 19.090 ns led_selout\[3\] 3 PIN PIN_F2 0 " "Info: 3: + IC(1.532 ns) + CELL(2.124 ns) = 19.090 ns; Loc. = PIN_F2; Fanout = 0; PIN Node = 'led_selout\[3\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.656 ns" { Mux~296 led_selout[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns 21.91 % " "Info: Total cell delay = 4.183 ns ( 21.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.907 ns 78.09 % " "Info: Total interconnect delay = 14.907 ns ( 78.09 % )" {  } {  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "19.090 ns" { b[1] Mux~296 led_selout[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.090 ns" { b[1] b[1]~out0 Mux~296 led_selout[3] } { 0.000ns 0.000ns 13.375ns 1.532ns } { 0.000ns 1.469ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "cqi\[1\] en clk -5.793 ns register " "Info: th for register \"cqi\[1\]\" (data pin = \"en\", clock pin = \"clk\") is -5.793 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.109 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J16 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.711 ns) 3.109 ns cqi\[1\] 2 REG LC_X6_Y13_N7 13 " "Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi\[1\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.640 ns" { clk cqi[1] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.12 % " "Info: Total cell delay = 2.180 ns ( 70.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.929 ns 29.88 % " "Info: Total interconnect delay = 0.929 ns ( 29.88 % )" {  } {  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[1] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.917 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 PIN PIN_P3 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_P3; Fanout = 4; PIN Node = 'en'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { en } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.581 ns) + CELL(0.867 ns) 8.917 ns cqi\[1\] 2 REG LC_X6_Y13_N7 13 " "Info: 2: + IC(6.581 ns) + CELL(0.867 ns) = 8.917 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi\[1\]'" {  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "7.448 ns" { en cqi[1] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 26.20 % " "Info: Total cell delay = 2.336 ns ( 26.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.581 ns 73.80 % " "Info: Total interconnect delay = 6.581 ns ( 73.80 % )" {  } {  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "8.917 ns" { en cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.917 ns" { en en~out0 cqi[1] } { 0.000ns 0.000ns 6.581ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[1] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "8.917 ns" { en cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.917 ns" { en en~out0 cqi[1] } { 0.000ns 0.000ns 6.581ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 9 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 21 11:20:00 2008 " "Info: Processing ended: Fri Nov 21 11:20:00 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}