📄 cnt10.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "led7s\[3\]\$latch " "Info: Node \"led7s\[3\]\$latch\"" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0} } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "led7s\[2\]\$latch " "Info: Node \"led7s\[2\]\$latch\"" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0} } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "led7s\[1\]\$latch " "Info: Node \"led7s\[1\]\$latch\"" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0} } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "led7s\[0\]\$latch " "Info: Node \"led7s\[0\]\$latch\"" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0} } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 34 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cqi\[0\] cqi\[2\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"cqi\[0\]\" and destination register \"cqi\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.462 ns + Longest register register " "Info: + Longest register to register delay is 1.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cqi\[0\] 1 REG LC_X6_Y13_N2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi\[0\]'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cqi[0] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.738 ns) 1.462 ns cqi\[2\] 2 REG LC_X6_Y13_N5 12 " "Info: 2: + IC(0.724 ns) + CELL(0.738 ns) = 1.462 ns; Loc. = LC_X6_Y13_N5; Fanout = 12; REG Node = 'cqi\[2\]'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.462 ns" { cqi[0] cqi[2] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 50.48 % " "Info: Total cell delay = 0.738 ns ( 50.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.724 ns 49.52 % " "Info: Total interconnect delay = 0.724 ns ( 49.52 % )" { } { } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.462 ns" { cqi[0] cqi[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.462 ns" { cqi[0] cqi[2] } { 0.000ns 0.724ns } { 0.000ns 0.738ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.109 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J16 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.711 ns) 3.109 ns cqi\[2\] 2 REG LC_X6_Y13_N5 12 " "Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N5; Fanout = 12; REG Node = 'cqi\[2\]'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.640 ns" { clk cqi[2] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.12 % " "Info: Total cell delay = 2.180 ns ( 70.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.929 ns 29.88 % " "Info: Total interconnect delay = 0.929 ns ( 29.88 % )" { } { } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[2] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.109 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J16 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.711 ns) 3.109 ns cqi\[0\] 2 REG LC_X6_Y13_N2 13 " "Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N2; Fanout = 13; REG Node = 'cqi\[0\]'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.640 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.12 % " "Info: Total cell delay = 2.180 ns ( 70.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.929 ns 29.88 % " "Info: Total interconnect delay = 0.929 ns ( 29.88 % )" { } { } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[0] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[2] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[0] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.462 ns" { cqi[0] cqi[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.462 ns" { cqi[0] cqi[2] } { 0.000ns 0.724ns } { 0.000ns 0.738ns } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[2] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[0] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { cqi[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { cqi[2] } { } { } } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "cqi\[1\] en clk 5.845 ns register " "Info: tsu for register \"cqi\[1\]\" (data pin = \"en\", clock pin = \"clk\") is 5.845 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.917 ns + Longest pin register " "Info: + Longest pin to register delay is 8.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 PIN PIN_P3 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_P3; Fanout = 4; PIN Node = 'en'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { en } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.581 ns) + CELL(0.867 ns) 8.917 ns cqi\[1\] 2 REG LC_X6_Y13_N7 13 " "Info: 2: + IC(6.581 ns) + CELL(0.867 ns) = 8.917 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi\[1\]'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "7.448 ns" { en cqi[1] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 26.20 % " "Info: Total cell delay = 2.336 ns ( 26.20 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.581 ns 73.80 % " "Info: Total interconnect delay = 6.581 ns ( 73.80 % )" { } { } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "8.917 ns" { en cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.917 ns" { en en~out0 cqi[1] } { 0.000ns 0.000ns 6.581ns } { 0.000ns 1.469ns 0.867ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.109 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J16 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J16; Fanout = 4; CLK Node = 'clk'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.711 ns) 3.109 ns cqi\[1\] 2 REG LC_X6_Y13_N7 13 " "Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X6_Y13_N7; Fanout = 13; REG Node = 'cqi\[1\]'" { } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "1.640 ns" { clk cqi[1] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "E:/实验8/cnt10.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.12 % " "Info: Total cell delay = 2.180 ns ( 70.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.929 ns 29.88 % " "Info: Total interconnect delay = 0.929 ns ( 29.88 % )" { } { } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[1] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "8.917 ns" { en cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.917 ns" { en en~out0 cqi[1] } { 0.000ns 0.000ns 6.581ns } { 0.000ns 1.469ns 0.867ns } } } { "E:/实验8/db/cnt10_cmp.qrpt" "" { Report "E:/实验8/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "E:/实验8/db/cnt10.quartus_db" { Floorplan "E:/实验8/" "" "3.109 ns" { clk cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { clk clk~out0 cqi[1] } { 0.000ns 0.000ns 0.929ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
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