cnt10.map.rpt

带复位和时钟使能的十进制计数器 verilo 描述

+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 28        ;
; Total combinational functions   ; 28        ;
;     -- Total 4-input functions  ; 12        ;
;     -- Total 3-input functions  ; 16        ;
;     -- Total 2-input functions  ; 0         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 4         ;
; I/O pins                        ; 29        ;
; Maximum fan-out node            ; cqi[1]    ;
; Maximum fan-out                 ; 13        ;
; Total fan-out                   ; 124       ;
; Average fan-out                 ; 2.18      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |cnt10                     ; 28 (28)     ; 4            ; 0           ; 29   ; 0            ; 24 (24)      ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |cnt10              ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; led7s[0]$latch                                ;   ;
; led7s[1]$latch                                ;   ;
; led7s[2]$latch                                ;   ;
; led7s[3]$latch                                ;   ;
; led7s[4]$latch                                ;   ;
; led7s[5]$latch                                ;   ;
; led7s[6]$latch                                ;   ;
; Number of user-specified and inferred latches ; 7 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/实验8/cnt10.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Nov 21 11:19:39 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt10 -c cnt10
Info: Found 2 design units, including 1 entities, in source file cnt10.vhd
    Info: Found design unit 1: cnt10-bhh
    Info: Found entity 1: cnt10
Info: Elaborating entity "cnt10" for the top level hierarchy
Info: VHDL Case Statement information at cnt10.vhd(63): OTHERS choice is never selected
Warning: VHDL Process Statement warning at cnt10.vhd(34): signal or variable "led7s" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "led7s" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Latch led7s[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Latch led7s[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Latch led7s[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Latch led7s[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Latch led7s[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Latch led7s[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Latch led7s[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cqi[0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "cout[0]" stuck at VCC
    Warning: Pin "cout[1]" stuck at VCC
    Warning: Pin "cout[2]" stuck at VCC
    Warning: Pin "cout[3]" stuck at VCC
    Warning: Pin "cout[4]" stuck at VCC
    Warning: Pin "cout[5]" stuck at VCC
    Warning: Pin "cout[6]" stuck at VCC
Info: Implemented 57 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 23 output pins
    Info: Implemented 28 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings
    Info: Processing ended: Fri Nov 21 11:19:41 2008
    Info: Elapsed time: 00:00:03