ddr_top.v

DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
//                     5555 NE Moore Court
//                     Hillsboro, OR 97214
//                     U.S.A
//
//                     TEL: 1-800-Lattice (USA and Canada)
//                          408-826-6000 (other locations)
//
//                     web: http://www.latticesemi.com/
//                     email: [e-mail]
//
// --------------------------------------------------------------------
//
// This is the main control module of the SDR SDRAM controller
// reference design.
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V0.1 :| Nagaraj Chekka    :| 07/28/03  :| Pre-Release
// --------------------------------------------------------------------
`timescale 1ns / 1ps
module ddr_top (
                //Inout
                ddr_dq,
                ddr_dqs,
                sysd,
                // Outputs
                sys_rdyn, 
                sys_init_done,  
                ddr_dqm, 
                ddr_wen, 
                ddr_rasn, 
                ddr_csn, 
                ddr_cke, 
                ddr_casn, 
                ddr_ba, 
                ddr_add, 
                ddr_clk, 
                ddr_clkn,
                // Inputs
                sys_r_wn, 
                sys_dmsel, 
                sys_dly_200us,  
                sys_adsn, 
                sys_add, 
                reset_n, 
                clk
                );

`include "ddr_par.v"


input                   clk;             // System clk
input                   reset_n;         // System reset
input [RA_MSB:CA_LSB]   sys_add;         // System address 
input                   sys_adsn;        // System address strobe
input                   sys_dly_200us;   // Signal from system to be asseted after 200us of stable clk
input [DSIZE/8-1:0]     sys_dmsel;       // System data mask select during DDR write
input                   sys_r_wn;        // Read (high) and write low

output [DDR_A_WIDTH-1:0]ddr_add;         // DDR address
output [DDR_BA_WIDTH-1:0]ddr_ba;         // DDR bank address
output                  ddr_casn;        // DDR cas signal
output                  ddr_cke;         // DDR clock enable
output                  ddr_csn;         // DDR chip select
output                  ddr_rasn;        // DDR rasn
output                  ddr_wen;         // DDR write enable
output [DSIZE/16-1:0]   ddr_dqm;         // DDR data mask signal
output                  sys_init_done;   // DDR intialsation done
output                  sys_rdyn;        // Ready signal to system
output                  ddr_clk;         // DDR clock
output                  ddr_clkn;        // DDR clock -ve

inout [DSIZE/2-1:0]     ddr_dq;          // DDR data in/out
inout [DSIZE/16-1:0]    ddr_dqs;         // DDR data strobe
inout [DSIZE-1:0]       sysd;            // System data in/out


reg [DSIZE/2-1:0]       ddr_dq_i;
reg [DSIZE/16-1:0]      ddr_dqs_i;
reg [DSIZE-1:0]         sysd_i;

wire [RA_MSB:CA_LSB]    addr;                 
wire [3:0]              cstate;               
wire [3:0]              istate;               
wire                    wren;                 
wire [DSIZE-1:0]        sys_datain;           
wire [DSIZE/2-1:0]      dqout;                
wire [DSIZE/2-1:0]      dqout_en;             
wire [DSIZE/16-1:0]     dqsout;               
wire [DSIZE/2-1:0]      dqin;                 
wire [DSIZE/16-1:0]     dqsout_en;            
wire [DSIZE-1:0]        sys_dataout;          
wire [DSIZE-1:0]        sys_dataout_en;       
wire 			pll_mclk_sp;


integer                 i,j,m;

ddr_ctrl u1_ddr_ctrl (
                      /*AUTOINST*/
                      // Outputs
                      .sys_init_done    (sys_init_done),
                      .istate           (istate[3:0]),
                      .cstate           (cstate[3:0]),
                      .wren             (wren),
                      .addr             (addr[RA_MSB:CA_LSB]),
                      // Inputs
                      .clk              (pll_mclk),
                      .reset_n          (reset_n),
                      .sys_r_wn         (sys_r_wn),
                      .sys_adsn         (sys_adsn),
                      .sys_dly_200us    (sys_dly_200us),
                      .sys_add          (sys_add[RA_MSB:CA_LSB]));


ddr_data u1_ddr_data (
                      /*AUTOINST*/
                      // Outputs
                      .dqout_en         (dqout_en[DSIZE/2-1:0]),
                      .dqout            (dqout[DSIZE/2-1:0]),
                      .dqsout_en        (dqsout_en[DSIZE/16-1:0]),
                      .dqsout           (dqsout[DSIZE/16-1:0]),
                      .sys_rdyn         (sys_rdyn),
                      .sys_dataout      (sys_dataout[DSIZE-1:0]),
                      .sys_dataout_en   (sys_dataout_en[DSIZE-1:0]),
                      .dqm_out          (ddr_dqm[DSIZE/16-1:0]),
                      // Inputs
                      .clk              (pll_mclk),
                      .clk2x            (pll_nclk),
                      .reset_n          (reset_n),
                      .cstate           (cstate[3:0]),
                      .wren             (wren),
                      .sys_datain       (sys_datain[DSIZE-1:0]),
                      .sys_dmsel        (sys_dmsel[DSIZE/8-1:0]),
                      .dqin             (dqin[DSIZE/2-1:0]));


ddr_sig u1_ddr_sig   (
                      /*AUTOINST*/
                      // Outputs
                      .ddr_cke          (ddr_cke),
                      .ddr_csn          (ddr_csn),
                      .ddr_rasn         (ddr_rasn),
                      .ddr_casn         (ddr_casn),
                      .ddr_wen          (ddr_wen),
                      .ddr_ba           (ddr_ba[DDR_BA_WIDTH-1:0]),
                      .ddr_add          (ddr_add[DDR_A_WIDTH-1:0]),
                      // Inputs
                      .clk              (pll_mclk),
                      .reset_n          (reset_n),
                      .addr             (addr[RA_MSB:CA_LSB]),
                      .istate           (istate[3:0]),
                      .cstate           (cstate[3:0]));



//assign ddr_clk   = pll_mclk;
//assign ddr_clkn  = !pll_mclk;

assign ddr_clk   = pll_mclk_sp;
assign ddr_clkn  = !pll_mclk_sp;


ddr_pll_orca  u1_ddr_pll_orca(
                              .clk    (clk),
                              .mclk   (pll_mclk),
                              .nclk   (pll_nclk),
                              .lock   (lock)
                              );


ddr_pll_orca_sp  u2_ddr_pll_orca(
				 .clk    (clk),
				 .mclk   (pll_mclk_sp),
				 .nclk   (),
				 .lock   ()
				 );



//===============================================================
// DDR interface (READ & WRITE
//===============================================================

// Read data
assign  dqin[DSIZE/2-1:0]        = ddr_dq;                     

// Write data
always @ (dqout_en or dqout) begin
   for (i=0; i<(DSIZE/2); i=i+1)
     // For ORCA
     ddr_dq_i[i]     = dqout_en[i] ? 1'bz : dqout[i] ;

   // FOr XPGA
   // ddr_dq_i[i]     = dqout_en[i] ? dqout[i] : 1'bz ;
end

assign #(0.9) ddr_dq = ddr_dq_i;

always @ (dqsout_en or dqsout) begin
   for (j=0; j<(DSIZE/16); j=j+1)
     // For ORCA
     ddr_dqs_i[j]    = dqsout_en[j] ? 1'bz : dqsout[j];

   //For XPGA
   //ddr_dqs_i[j]    = dqsout_en[j] ? dqsout[j] : 1'bz;
end
assign #(0.9) ddr_dqs = ddr_dqs_i;

//===============================================================
// System side interface
//===============================================================

// Write (system write)
assign  sys_datain[DSIZE-1:0]        = sysd;


// System Read
always @ (sys_dataout_en or sys_dataout) begin
   for (m=0; m<DSIZE; m=m+1)
     // For ORCA
     sysd_i[m]     = sys_dataout_en[m] ? 1'bz : sys_dataout[m] ;

     // For XPGA
     // sysd_i[m]     = sys_dataout_en[m] ? sys_dataout[m] : 1'bz ;
end
assign #(0.9) sysd = sysd_i;



endmodule