stimulus.v

DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
//                     5555 NE Moore Court
//                     Hillsboro, OR 97214
//                     U.S.A
//
//                     TEL: 1-800-Lattice (USA and Canada)
//                          408-826-6000 (other locations)
//
//                     web: http://www.latticesemi.com/
//                     email: [e-mail]
//
// --------------------------------------------------------------------
//
// This is the main control module of the SDR SDRAM controller
// reference design.
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V0.1 :| Nagaraj Chekka    :| 07/23/03  :| Pre-Release
// --------------------------------------------------------------------

`timescale 1ns / 1ps
module stimulus
  (
   clk,
   reset_n,
   sys_add,
   sys_adsn,
   sys_r_wn,
   sysd,
   sys_dmsel,
   sys_dly_200us,
   sys_init_done,
   sys_rdyn
   );

`include "ddr_par.v"

//---------------------------------------------------------------------
// outputs & registers
//
output                      clk;
output                      reset_n;
output [RA_MSB:CA_LSB]      sys_add;
output                      sys_adsn;
output                      sys_r_wn;
output                      sys_dly_200us;
output                      sys_rdyn;
output [DSIZE/8-1:0]        sys_dmsel;

input                       sys_init_done;

inout [DSIZE-1:0]           sysd;

reg                         clk_int;
reg                         clk_en;
reg                         reset_n;
reg [RA_MSB:CA_LSB]         sys_add;
reg                         sys_adsn;
reg                         sys_r_wn;
reg [DSIZE-1:0]             sysd_i;
reg [DSIZE/8-1:0]           sys_dmsel;
reg                         write_en;
reg                         sys_dly_200us;

wire                        clk;
wire [DSIZE-1:0]            sysd;
reg [2:0]                   add_i;

reg [CA_MSB-CA_LSB:0]       col_gen;
reg [BA_MSB-BA_LSB:0]       ba_gen;
reg [RA_MSB-RA_LSB:0]       row_gen;

reg [DSIZE-1:0]             data_gen;
wire [DSIZE-1:0] 	    sysd_read;


integer                     ik;
   

//=============================================================================
// parameters -- change to whatever you like
//=============================================================================

parameter clock_time = 100;
parameter reset_time = 1000;
parameter clk_period = tCK;

//---------------------------------------------------------------------
// tasks
//
task write;
   input [RA_MSB:CA_LSB] addr;
   input [DSIZE-1:0] data;
   begin
      #1;
      
      sys_add    =  addr;
      sys_adsn   =  0;
      sys_r_wn   =  0;
      write_en   =  1'b1;
      #clk_period;
      sys_adsn   =  1;
      sysd_i     =  data;
      add_i      =  0;
      
      // Depending upon the burst length
      // NUM_CLK_WRITE can be 2, 4 and 8
      wait (!sys_rdyn);
      #1;

      $display ("Write data %h", data);
      
      repeat (NUM_CLK_WRITE-1) begin
         @ (posedge clk);
         #1;
         add_i   =   add_i + 1'b1;
         sysd_i  =  data + add_i;
      end
      
      wait (sys_rdyn);
      
      
      //#(clk_period * (num_clk_write + num_clk_wait + 4));
      sysd_i     =  {DSIZE {1'bz}};
      write_en   =  1'b0;
      sys_r_wn   =  1;
      sys_add    =  {RA_MSB+1{1'bz}};
   end
endtask

task read;
   input [RA_MSB:CA_LSB] addr;
   input [DSIZE-1:0] data;
   begin
      #1;
      
      sys_add    =  addr;
      sys_adsn   =  0;
      sys_r_wn   =  1;
      #clk_period;
      sys_adsn   =  1;
      add_i      =  0;
      
      // Depending upon the burst length
      // NUM_CLK_READ can be 2, 4 and 8

      wait (!sys_rdyn);
      #1;
      
      repeat (NUM_CLK_READ) begin
         @ (posedge clk);
         if (sysd_read === (data + add_i)) $display ("At %t, DATA READ=%h", $time, sysd_read);
         else $display ("ERROR: At %t, DATA READ=%h, DATA SHOULD BE=%h", $time, sysd_read, (data + add_i));
         add_i  = (add_i + 1'b1);
      end
      wait (sys_rdyn);
      sys_r_wn   =  1;
      sys_add    =  {RA_MSB+1{1'bz}};
  end
endtask


assign sysd = write_en ? sysd_i : {DSIZE {1'bz}};


//---------------------------------------------------------------------
// code
//
initial begin
   sys_r_wn         <= #1 1'b1;
   sys_adsn         <= #1 1'b1;
   sys_dly_200us    <= #1 1'b0;
   clk_int          <= #1 1'b0;
   reset_n          <= #1 1'b0;
   sys_add          <= #1 {RA_MSB+1 {1'b1}};
   sysd_i           <= #1 {DSIZE {1'bz}};
   sys_dmsel        <= #1 {DSIZE/8 {1'b0}};
   clk_en           <= #1 1'b0;
   write_en         <= #1 1'b0;
   #clock_time;
   clk_en           <= #1 1'b1;
   #reset_time;
   @(posedge clk);
   $display($time,"ns : coming out of reset");
   reset_n          <= #1 1'b1;
   // #200000;
   #200   ;
   sys_dly_200us    <= #1 1'b1;
   @(posedge sys_init_done);
   #500;
   repeat (210) @ (posedge clk);
   @(negedge clk);

   
   ik = 0;
   data_gen = {DSIZE {1'b0}};

   col_gen = {CA_MSB-CA_LSB {1'b0}};
   ba_gen = {BA_MSB-BA_LSB {1'b0}};
   row_gen = {RA_MSB-RA_LSB {1'b0}};
   
   repeat (100) begin
      row_gen = row_gen + 1;
      ba_gen = ba_gen + 1'b1;

      write({row_gen,ba_gen, col_gen+10'h000}, data_gen);
      write({row_gen,ba_gen, col_gen+10'h100}, (data_gen+1*NUM_CLK_WRITE));
      write({row_gen,ba_gen, col_gen+10'h200}, (data_gen+2*NUM_CLK_WRITE));
      write({row_gen,ba_gen, col_gen+10'h300}, (data_gen+3*NUM_CLK_WRITE));

      read({row_gen,ba_gen, col_gen+10'h000}, data_gen);
      read({row_gen,ba_gen, col_gen+10'h100}, (data_gen+1*NUM_CLK_READ));
      read({row_gen,ba_gen, col_gen+10'h200}, (data_gen+2*NUM_CLK_READ));
      read({row_gen,ba_gen, col_gen+10'h300}, (data_gen+3*NUM_CLK_READ));
      
      
      ik = ik +1;
      data_gen = data_gen + 4*NUM_CLK_READ + 1;      
   end
   $finish;
end

always 
    #(clk_period/2.0) clk_int <= ~clk_int;

assign clk = clk_en & clk_int;
assign #(2.5) sysd_read =  sysd;


endmodule