clk_div.v

一个时钟分频模块,in verilog hdl

/*
clk_div clk_div(
    clk     ( clk ),    // frequency is 50MHz
    rst_n   ( rst_n ),  // asynchronous, low asserted

    clk_1m  ( clk_1m ), // width of the pulse is one clock period
    clk_1k  ( clk_1k ), // width of the pulse is one clock period
    clk_1hz ( clk_1hz ) // width of the pulse is one clock period
);
*/


module clk_div (
    input             clk,    // frequency is 50MHz
    input             rst_n,  // asynchronous, low asserted
    
    output reg        clk_1m, // width of the pulse is one clock period
    output reg        clk_1k, // width of the pulse is one clock period
    output reg        clk_1hz // width of the pulse is one clock period
);

reg       [5:0]   cnt_1m;                       // 50
reg       [9:0]   cnt_1k;                       // 1000
reg       [9:0]   cnt_1hz;                      // 1000

/*
 * clk_1m
 */

always @( posedge clk or negedge rst_n ) begin
    if ( ~rst_n )
        cnt_1m <= 1'b0;
    else if ( cnt_1m < 6'd49 )
        cnt_1m <= cnt_1m + 6'd1;
    else
        cnt_1m <= 1'b0;
end

always @( posedge clk or negedge rst_n ) begin
    if ( ~rst_n )
        clk_1m <= 1'b0;
    else if ( cnt_1m == 6'd49 )
        clk_1m <= 1'b1;
    else 
        clk_1m <= 1'b0;
end

/*
 * clk_1k
 */
always @( posedge clk or negedge rst_n ) begin
    if ( ~rst_n )
        cnt_1k <= 1'b0;
    else if ( clk_1m) begin
        if ( cnt_1k < 10'd999 )
            cnt_1k <= cnt_1k + 10'd1;
        else
            cnt_1k <= 1'b0;
    end
end

always @( posedge clk or negedge rst_n ) begin
    if ( ~rst_n )
        clk_1k <= 1'b0;
    else if ( clk_1m && (cnt_1k == 10'd999) )
        clk_1k <= 1'b1;
    else 
        clk_1k <= 1'b0;
end

/*
 * clk_1hz
 */
always @( posedge clk or negedge rst_n ) begin
    if ( ~rst_n )
        cnt_1hz <= 1'b0;
    else if ( clk_1k) begin
        if ( cnt_1hz < 10'd999 )
            cnt_1hz <= cnt_1hz + 10'd1;
        else
            cnt_1hz <= 1'b0;
    end
end

always @( posedge clk or negedge rst_n ) begin
    if ( ~rst_n )
        clk_1hz <= 1'b0;
    else if ( clk_1k && (cnt_1hz == 10'd999) )
        clk_1hz <= 1'b1;
    else 
        clk_1hz <= 1'b0;
end

endmodule