m1.v

用verilog设计一个简单的cpu系统

module ram(data,addr,read,write);
inout[7:0]data;
input[10:0]addr;
input read,write;
reg [7:0]ram[1023:0];
assign data=(read)? ram[addr]:8'bzzzzzzzz;
always @(write or data)
	if(write) ram[addr]<=data;
/*always @(posedge write)
begin
ram[addr]<=data;
end*/
endmodule