cpu.v

用verilog设计一个简单的cpu系统

module cpu(data,clk,rst,read,write,addr);
inout[7:0]data;
input clk, rst;
output read,write;
output [15:0]addr; 
wire [7:0]data;



//the control signals define
wire read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem;
wire[6:0] alus;
wire[15:0] dbus,pcdbus;
wire[7:0]drdbus,trdbus,rdbus,acdbus;
wire[7:0]irout;
wire[7:0]aluout;
wire zin,zout;
assign zin=~|aluout;

ar mar(dbus,clk,rst,arload,arinc,addr);

pc mpc(dbus,clk,rst,pcload,pcinc,pcdbus);

dr mdr(dbus[7:0],clk,rst,drload,drdbus);

tr mtr(drdbus,clk,rst,trload,trdbus);

ir mir(drdbus,clk,rst,irload,irout);

r mr(dbus[7:0],clk,rst,rload,rdbus);

ac mac(aluout,clk,rst,acload,acdbus);

alu malu(alus,acdbus,dbus,aluout);

z mz(zin,clk,rst,zload,zout);

control mcont(irout,clk,rst,zout,read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,alus,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem);

//allocate dbus
assign dbus[15:0]=(pcbus)?pcdbus[15:0]:16'bzzzzzzzzzzzzzzzz;
assign dbus[15:8]=(drhbus)?drdbus[7:0]:8'bzzzzzzzz;
assign dbus[7:0]=(drlbus)?drdbus[7:0]:8'bzzzzzzzz;
assign dbus[7:0]=(trbus)?trdbus[7:0]:8'bzzzzzzzz;
assign dbus[7:0]=(rbus)?rdbus[7:0]:8'bzzzzzzzz;
assign dbus[7:0]=(acbus)?acdbus[7:0]:8'bzzzzzzzz;  

assign dbus[7:0]=(membus)?data[7:0]:8'bzzzzzzzz;
assign data[7:0]=(busmem)?dbus[7:0]:8'bzzzzzzzz;


endmodule