expcomp.vhd

基于VHDL语言的32位单精度的浮点加法器

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity EXPCOMP is
    port (
        XEXP: in std_logic_vector (7 downto 0);
        YEXP: in std_logic_vector (7 downto 0);
        BIGX:   out std_logic;
        TOOSMALL:   out std_logic;
        SHIFTD: out std_logic_vector (4 downto 0);
        BIGEXP: out std_logic_vector (7 downto 0)
         );
end EXPCOMP;

architecture RTL of EXPCOMP is
signal X_Y, Y_X, SHIFTCNT: std_logic_vector (8 downto 0);
signal BIGXsig : std_logic;
signal SIGN2 : std_logic_vector (1 downto 0);

begin

X_Y <= (Xexp(7) & Xexp) - (Yexp(7) & Yexp);
Y_X <= (Yexp(7) & Yexp) - (Xexp(7) & Xexp);
SIGN2 <= Xexp(7) & Yexp(7);

with SIGN2 select
     BIGXsig <= not X_Y(8) when "00", '1' when "01", '0' when "10", X_Y(8) when others;
     BIGEXP <= Xexp when BIGXsig = '1' else Yexp;
     SHIFTCNT <= X_Y when BIGXsig = '1' else Y_X;
     SHIFTD <= SHIFTCNT(4 downto 0);
     TOOSMALL <= SHIFTCNT(8) or SHIFTCNT(7) or SHIFTCNT(6) or SHIFTCNT(5);
     BIGX <= BIGXsig;

end RTL;