ext2_25to32.vhd

来自「基于VHDL语言的32位单精度的浮点加法器」· VHDL 代码 · 共 17 行

Library IEEE;
use IEEE.std_logic_1164.all;

entity EXT2_25to32 is
    port (
        MANSUM25: in std_logic_vector (24 downto 0);
        LEFTDIN  : out std_logic_vector (31 downto 0)
         );
end EXT2_25to32;

architecture RTL of EXT2_25to32 is

begin

LEFTDIN <= "0000000" & MANSUM25;

end RTL;