count_deng.map.qmsg

用VHDL语言实现8421码的十进制计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 23 08:56:59 2009 " "Info: Processing started: Sat May 23 08:56:59 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off count_deng -c count_deng " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off count_deng -c count_deng" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count_deng.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count_deng.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count_deng-a " "Info: Found design unit 1: count_deng-a" {  } { { "D:/第三周  试验  07607邓习海/count_deng.vhd" "count_deng-a" "" { Text "D:/第三周  试验  07607邓习海/count_deng.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 count_deng " "Info: Found entity 1: count_deng" {  } { { "D:/第三周  试验  07607邓习海/count_deng.vhd" "count_deng" "" { Text "D:/第三周  试验  07607邓习海/count_deng.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clr count_deng.vhd(21) " "Warning: VHDL Process Statement warning at count_deng.vhd(21): signal clr is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/count_deng.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q count_deng.vhd(30) " "Warning: VHDL Process Statement warning at count_deng.vhd(30): signal q is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/count_deng.vhd" 30 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "oc GND " "Warning: Pin oc stuck at GND" {  } { { "D:/第三周  试验  07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/count_deng.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "clr " "Info: Promoted clear signal driven by pin clr to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "12 " "Info: Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "5 " "Info: Implemented 5 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 23 08:57:02 2009 " "Info: Processing ended: Sat May 23 08:57:02 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}