count_deng.vhd

用VHDL语言实现8421码的十进制计数器

--dengxihai' jishuqi

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_deng is

port(
    
     clk:in std_logic;
     clr:in std_logic;
     oc:out std_logic;
     y: out std_logic_vector(3 downto 0)

);
end ;
architecture a of count_deng is

signal q: std_logic_vector(3 downto 0); 
begin
process(clk)
begin 
if clr='0'then 
q<="0000";            --qinglin

elsif (clk'event and clk ='1') then
if q="1001"  then 
    q<="0000";
     else q<=q+1;
    end if;
    end if;
    y<=q;
    end process;
    end;