ex_p6_19_mult18x18.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY unisim;
use unisim.VCOMPONENTS.all;
entity mult_tb is end mult_tb;
architecture Behavioral of mult_tb is
	signal P : std_logic_vector (35 downto 0);
	signal A:std_logic_vector(17 downto 0):=(others => '1');
   signal B:std_logic_vector(17 downto 0):=
                  ( 3 downto 0 => '1',others => '0');
	for all:MULT18X18 use entity unisim.MULT18X18;
begin
   process
       variable count:integer:=0;
   begin
       A <= (A(0) xor A(1)) &
                  A(17 downto 1);
       B <= (B(0) xor B(1)) &
                  B(17 downto 1);
       count := count + 1;
       wait for 50 ns;
       assert P = A * B  report "multiply error";
       if count < 20 then wait for 50 ns;
       else wait;
       end if;
    end process;
	M:MULT18X18 port map(P,A,B);
end Behavioral;