ex_p6_14_ba_test.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
entity BA_TEST is	end BA_TEST;
architecture BEH of BA_TEST is
    signal a,b,s:BIT_vector(7 downto 0);
    signal cin,cout:BIT;
begin
	B1:entity work.BA port map(a,b,cin,s,cout);
	process
	    VARIABLE lout: line;
	    variable expected_s:bit_vector(7 downto 0);
	begin
	    for i in 0 to 255 loop
	       for j in 0 to 255 loop
	          for k in BIT'('0') to BIT'('1') loop
	             cin <= k;
	             a <= to_bitvector(conv_std_logic_vector(i,8));
	             b <= to_bitvector(conv_std_logic_vector(j,8));
	             expected_s := to_bitvector
	                   (conv_std_logic_vector(i,8) + 
	                    conv_std_logic_vector(j,8) +
	                    to_stdulogic(k));
	             wait for 100 ns;
	             WRITE(lout, a);WRITE(lout, character'(' '));
                WRITE(lout, b);WRITE(lout, character'(' '));
                WRITE(lout,cin);WRITE(lout, character'(' '));
                WRITE(lout, s);WRITE(lout, character'(' '));
                WRITE(lout, expected_s);WRITE(lout, character'(' '));
                WRITE(lout, cout);WRITE(lout, character'(' '));
                WRITELINE(OUTPUT, lout);
            end loop;
        end loop;
    end loop;
end process;
end BEH;