ex6_2_filedemo2.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 29 行

--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.std_logic_textio.all;
use std.textio.all;
entity FILEDEMO2 is end FILEDEMO2;
architecture arch of FILEDEMO2 is
	type MEMORY is array(0 to 31)of bit_vector(7 downto 0);
	signal M:memory;
	
BEGIN
  PROCESS
	VARIABLE lout,lin: line ;
	file DATAFILE:text open READ_MODE is "RAM.TXT";
	--variable b:std_logic_vector(7 downto 0);
	variable b:bit_vector(7 downto 0);
  begin
	WRITE(lout, string'(" input"),LEFT,10) ;
	WRITE(lout, string'("Data"),LEFT,10) ;
   WRITELINE(OUTPUT, lout) ;
	for i in M'range loop
		if ENDFILE(DATAFILE) then exit;end if;
		readline(DATAFILE,lin);read(lin,b);
		WRITE(lout, i,LEFT,10) ;WRITE(lout, b,LEFT,10) ;
      WRITELINE(OUTPUT, lout) ;
      M(i) <= b;
	end loop;
	wait;
  END PROCESS;
END arch ;