ex6_4_testbench1.vhd

This is the course for VHDL programming

use std.textio.all;
entity ENCODER is
	generic(DELAY : time := 5 ns);
	port(I1, I2, I3, I4 : in BIT; MSB, LSB : out BIT ; ACTIVE : out BIT);
end ENCODER;
architecture BEHAV of ENCODER is
begin
	process(I1,I2,I3,I4)
	variable BIT1,BIT0 : BIT;
		begin
			ACTIVE <=  I1 or I2 or I3 or I4;
			if    I4='1' then BIT1 := '1';BIT0 := '1';
			elsif I3='1' then BIT1 := '1';BIT0 := '0';
			elsif I2='1' then BIT1 := '0';BIT0 := '1';
			else              BIT1 := '0';BIT0 := '0';
			end if;
			MSB <= BIT1 after DELAY;
			LSB <= BIT0 after DELAY;
		end process;
end BEHAV;

package TB is 
type THREE_CHANNEL_TRACE_ELEMENT is record
	CH1:BIT;
	CH0:BIT;
	ACT:BIT;
	AT :time;
end record;
type THREE_CHANNEL_TRACE_FILE is file of THREE_CHANNEL_TRACE_ELEMENT;
component ENCODER port(I1,I2,I3,I4: in BIT; MSB,LSB:out BIT; ACTIVE : out BIT);
end component;
constant BITS_IN_VECTOR:integer := 4;
subtype TEST_VECTOR is BIT_VECTOR(BITS_IN_VECTOR-1 downto 0);
end TB;
use std.textio.all;
entity TBENCH is
end TBENCH;
use work.tb.all;
architecture TB1 of TBENCH is
   constant NO_OF_VECTORS:integer :=5;
   type VECTOR_MEMORY is array(1 to NO_OF_VECTORS) of TEST_VECTOR;
   constant INPUT_VECTORS:VECTOR_MEMORY:=
					("1010","0010","1100","0110","1111");
   constant VECTOR_PERIOD:time := 100 ns;
   signal IN1,IN2,IN3,IN4:BIT;
   SIGNAL OUT1,OUT2,TB_ACT:BIT;
begin
	ENCODER1:ENCODER port map(IN1,IN2,IN3,IN4,OUT2,OUT1,TB_ACT);
	APPLY_VECTORS:process
	begin
		for J in 1 to NO_OF_VECTORS loop
			IN1<=INPUT_VECTORS(J)(0);
			IN2<=INPUT_VECTORS(J)(1);
			IN3<=INPUT_VECTORS(J)(2);
			IN4<=INPUT_VECTORS(J)(3);
			wait for VECTOR_PERIOD;
		end loop;
	assert false report "TEST COMPLETED";
	wait;
	end process APPLY_VECTORS;
	 RECORDER: process (OUT1, OUT2, TB_ACT)
file TRACE:THREE_CHANNEL_TRACE_FILE open WRITE_MODE is
"NEW_TRACE.DAT";
	file ASCII_TRACE: TEXT    open WRITE_MODE is "NEW_TRACE.TXT";
	variable SAMPLE:THREE_CHANNEL_TRACE_ELEMENT;
	variable ASCII_LINE:LINE;
	begin
		--Fill SAMPLE record with values
SAMPLE.CH1 := OUT2;
		SAMPLE.CH0 := OUT1;
		SAMPLE.ACT := TB_ACT;
		SAMPLE.AT  := NOW;
		--Write sample record to binary file
		write(TRACE,SAMPLE);
		--Write test bench signals to text file
		write(ASCII_LINE,OUT2,LEFT,10);
		write(ASCII_LINE,OUT1,LEFT,10);
		write(ASCII_LINE,TB_ACT,LEFT,10);
		write(ASCII_LINE,NOW,LEFT,10);
		writeline(ASCII_TRACE,ASCII_LINE);
	end process RECORDER;
end TB1;