ex_p6_12_bin_to_ascii.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
entity FILERDBIN is end FILERDBIN;
architecture arch of FILERDBIN is
BEGIN
  PROCESS
	VARIABLE lout,lin: line;
	type REC_T is record
         x:integer;
	      y:std_logic_vector(3 downto 0);
	      z:std_logic;
	      u:character;
	      v:real;
	 end record;
   type REC_FILE_T is file of REC_T;
   variable R:REC_T;
	file FILE_OBJ_R:REC_FILE_T;
	file FILE_OBJ_W:text open WRITE_MODE is "ASC_DATA.TXT";
	variable STAT:FILE_OPEN_STATUS;
  begin
      file_open (STAT, FILE_OBJ_R, "BIN_DATA");
      if STAT = OPEN_OK then 
         WRITE(lout, string'("File BIN_DATA opened"));
         WRITELINE(OUTPUT, lout);
       else
          WRITE(lout, string'("File BIN_DATA open error"));
          WRITELINE(OUTPUT, lout);
      end if;
	   while not endfile(FILE_OBJ_R) loop
			read(FILE_OBJ_R,R);
		   WRITE(lout, R.x,LEFT,3);
	      WRITE(lout, R.y,LEFT,5);
	      WRITE(lout, R.z,LEFT,2);
		   WRITE(lout, R.u,LEFT,2);
		   WRITE(lout, R.v,LEFT,15);
         WRITELINE(FILE_OBJ_W, lout);
      end loop;
	   WRITE(lout, string'("ASC file written\n"));
      WRITELINE(OUTPUT, lout);
      FILE_CLOSE(FILE_OBJ_W);
      FILE_CLOSE(FILE_OBJ_R);
	   wait;
  END PROCESS;
END arch ;