ex6_2_filedemo.vhd

This is the course for VHDL programming

entity filedemo1 is
end filedemo1;

architecture a of filedemo1 is
	type INT_FILE_T is file of integer;
	type NAMES_FILE_T is file of string;
	signal STATUS: FILE_OPEN_STATUS:=OPEN_OK;
	file INT_FILE: INT_FILE_T;
	file INT_FILE2 : INT_FILE_T;
	file NAMES_FILE: NAMES_FILE_T;
begin
	file_open(INT_FILE, 
		"C:\\INTEGERS.DAT",WRITE_MODE);
	assert STATUS = OPEN_OK report "File error";
	process
		variable i:integer;
		variable fname:
			string(1 to 9):="C:\\f.txt";
		variable STR:
			string(1 to 4):="ABCD";
	begin
		file_open(NAMES_FILE, 
		fname,WRITE_MODE);
		write(NAMES_FILE,"123" & CR& LF);
		write(NAMES_FILE,STR);
		file_close(NAMES_FILE);

		file_open(INT_FILE, 
		"C:\\INTEGERS.DAT",WRITE_MODE);
		assert STATUS = OPEN_OK report "File error";
		write(INT_FILE,123);
		write(INT_FILE,456);
		file_close(INT_FILE);
		file_open(INT_FILE2, 
		"C:\\INTEGERS.DAT");
		while not endfile(INT_FILE2) loop
			read(INT_FILE2,i);
			report integer'image(i);
		end loop;
		file_close(INT_FILE);
		wait;	
	end process;
end a;