ex_p6_17_crc.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
entity crc is
	port(rst,clk,enable,last_bit,d : in std_logic;
			crc_out:out std_logic_vector(31 downto 0));
end crc;
architecture a of crc is
	signal lfsr:std_logic_vector(31 downto 0);
	constant poly:std_logic_vector(31 downto 0):= X"04c11db7";
begin
	process(clk,rst,enable,last_bit,d,lfsr)
		variable ext_inbit:std_logic_vector(31 downto 0);
		variable inbit:std_logic;
	begin
		inbit := d xor lfsr(31);
		for i in 0 to 31 loop
			ext_inbit(i) := inbit;
		end loop;
		if rst = '1' then lfsr <= X"FFFFFFFF";
		elsif clk'event and clk = '1' then
			if enable = '1' then
					lfsr <= (lfsr(30 downto 0) & '0')
					     xor (ext_inbit and poly) ;
			end if;
		end if;
	end process;
	process(lfsr)
	begin
		for i in lfsr'range loop
			crc_out(i) <= not lfsr(lfsr'high -i);
		end loop;
	end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity crc_tb is end crc_tb;
architecture a of crc_tb is
	signal rst,clk,enable,last_bit,d:std_logic;
	signal crc_out:std_logic_vector(31 downto 0);
	component crc
		port(rst,clk,enable,last_bit,d : in std_logic;
			crc_out:out std_logic_vector(31 downto 0));
	end component;
begin
	c:crc port map(rst,clk,enable,last_bit,d,
			crc_out);
	process
		variable s:std_logic_vector(7 downto 0):=
				 "00110001"; -- ascii 1
	begin
		enable <= '0';last_bit <= '0';
		clk <= '0';
		rst <= '1';wait for 50 ns;rst <= '0';
		enable <= '1';
		for i in 1 to 9 loop
			for j in 0 to 7 loop
				d <= s(j);
				if (i=9) and (j = 7) then last_bit <= '1';
				end if;
				wait for 50 ns; clk <= '1';
				wait for 50 ns; clk <= '0';
			end loop;
			s := s + 1;
		end loop;
		enable <= '0';
		wait for 50 ns; clk <= '1';
		wait for 50 ns; clk <= '0';
		wait;
	end process;
end a;