ex_p4_24_switchtail.vhd

This is the course for VHDL programming

entity SWITCHTAIL is
	port(CLK,RST:in BIT;COUNT:out BIT_VECTOR(7 downto 0));
end SWITCHTAIL;
architecture DF of  SWITCHTAIL is
    signal IC: BIT_VECTOR(7 downto 0);
begin
	process(CLK,RST,IC)
	begin
		if RST = '1' then IC<="00000000";
		elsif CLK = '1' and CLK'event then
			IC<= not IC(0) & IC(7 downto 1);
			COUNT <= IC;
		end if;
	end process;
end DF;
entity SWITCHTAIL_TB is	-- Test bench entity never has ports
end SWITCHTAIL_TB;		-- It generates its own stimulus
architecture BEH of SWITCHTAIL_TB is
	signal CLK,RST:bit;			--Give stimulus here
	signal COUNT:bit_vector(7 downto 0);--Observe this signal
begin
	S:entity work.SWITCHTAIL 	-- Instantiate SWITCHTAIL as S
		 port map(CLK, RST, COUNT);
	RST <= '1', '0' after 20 ns;
	process
   	begin
       for i in 0 to 12 loop
          wait for 50 ns;CLK <= '1';
          wait for 50 ns;CLK <= '0';
      end loop;
      wait;
  end process;
end BEH;