ex_p4_27_edge_detect.vhd

This is the course for VHDL programming

--edge detector
entity EDGE_DET is
	port(D,CLK,RST:in BIT;
	     POS_EDGE,NEG_EDGE:out BIT);
end EDGE_DET;
architecture DF of  EDGE_DET is
    signal Q1,Q2: BIT;
begin
	process(CLK,RST)
	begin
		if RST = '1' then Q1<='0';Q2<='0';
		elsif CLK = '1' and CLK'event then
			Q1<= D;Q2 <= Q1;
		end if;
	end process;
	POS_EDGE <= Q1 and not Q2;
	NEG_EDGE <= not Q1 and  Q2;
end DF;
entity EDGE_TB is end EDGE_TB;
architecture BEH of EDGE_TB is
    signal CLK,RST,D,POS_EDGE,NEG_EDGE : BIT;
begin
    ED:entity work.EDGE_DET
       port map(D,CLK,RST,POS_EDGE,NEG_EDGE);
    RST <= '1', '0' after 20 ns;
    D <= '0', '1' after 100ns, '0' after 500ns;
	 process
   	begin
       for i in 0 to 12 loop
          wait for 50 ns;CLK <= '1';
          wait for 50 ns;CLK <= '0';
      end loop;
      wait;
  end process;
end BEH;