ex_p4_22_dual_seq_fsm.vhd

This is the course for VHDL programming

--FINITE STATE MACHINE TO DETECT 
-- either a ?10111? or ?11001? sequence.
--Overlapping sequences are  allowed 
entity FSM_DUAL_SEQ is
	port(RST,X,CLK :in BIT; Z: out BIT);
end FSM_DUAL_SEQ;
architecture DF of FSM_DUAL_SEQ is
	type STATE_TABLE is(INIT,GOT1,GOT10,GOT101,
	      GOT1011,GOT11,GOT110,GOT1100);
	signal STATE,NEXT_STATE : STATE_TABLE;
begin
	process(CLK,RST,X)
	begin
	if(RST='1')then STATE <= INIT;
	elsif(CLK'event and CLK='1') then
		STATE<=NEXT_STATE;
	end if;
end process;
NEXT_STATE <= 
    GOT1    	   when STATE=INIT         and X='1' else
	 INIT    	   when STATE=INIT         and X='0' else
	 GOT1    	   when STATE=GOT1         and X='1' else
	 GOT10   	   when STATE=GOT1         and X='0' else
	 GOT101  	   when STATE=GOT10        and X='1' else
	 INIT    	   when STATE=GOT10        and X='0' else
	 GOT1011 	   when STATE=GOT101       and X='1' else
	 GOT10   	   when STATE=GOT101       and X='0' else
	 GOT11   	   when STATE=GOT1011      and X='1' else
	 GOT110  	   when STATE=GOT1011      and X='0' else
	 GOT11       when STATE=GOT11        and X='1' else
	 GOT110      when STATE=GOT11        and X='0' else
	 GOT101      when STATE=GOT110       and X='1' else
	 GOT1100     when STATE=GOT110       and X='0' else
	 GOT1        when STATE=GOT1100      and X='1' else
	 INIT    	   when STATE=GOT1100      and X='0' else
	 INIT ;
Z <= '1' when ((STATE= GOT1011) and (X='1'))else
     '1' when ((STATE= GOT1100) and (X='1'))else
    	'0';
end DF;