ex_4_3_mux.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 35 行

--Entity has been defined in ex_4_2_1mux_cond
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4_1 is
   Port(I0,I1,I2,I3,S0,S1:in std_logic;Y:out std_logic);
end mux4_1;
architecture DF_SEL of mux4_1 is
	signal s: std_logic_vector(1 downto 0);
begin
	s <= s1 & s0;
with s select
Y <=	 I0 after 5 ns when "00",
      I1 after 5 ns when "01",
      I2 after 5 ns when "10",
      I3 after 5 ns when "11",
      'X' after 5 ns when others;
end DF_SEL;
architecture DF_SEL2 of mux4_1 is
	signal s: std_logic_vector(1 downto 0);
begin
	s <= s1 & s0;
with s select
Y <=	 I0 after 5 ns when "00",
      I1 after 5 ns when "01"|"0Z",
      I2 after 5 ns when "10"|"Z0",
      I3 after 5 ns when "11"|"ZZ"|"Z1"|"1Z",
      'X' after 5 ns when others;
end DF_SEL2;
architecture DF2 of MUX4_1 is
begin
	Y<= I0 after 5 ns when S1='0' and S0='0' else 'Z' after 5 ns;
	Y<= I1 after 5 ns when S1='0' and S0='1' else 'Z' after 5 ns;	
	Y<= I2 after 5 ns when S1='1' and S0='0' else 'Z' after 5 ns;
	Y<= I3 after 5 ns when S1='1' and S0='1' else 'Z' after 5 ns;
end DF2;