ex_p4_17_two_port_ram.vhd

This is the course for VHDL programming

--TWO PORT RAM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity RAM2P is
	port (ADR_IN: in std_logic_vector(9 downto 0):=(OTHERS=>'0');
	      ADR_OUT:in std_logic_vector(9 downto 0):=(OTHERS=>'0');
		   CS_BAR, WR_BAR:in std_logic;
		   Din  :in std_logic_vector(7 downto 0);
		   Dout :out std_logic_vector(7 downto 0));
	constant acc_time:time:=50 ns;
end RAM2P ;

architecture DATAFLOW of RAM2P  is
type RAM_ARRAY is array(0 to 1023) of std_logic_vector(7 downto 0);
signal RAM:RAM_ARRAY;
begin
	Dout<=RAM(conv_integer(ADR_OUT)) after acc_time when CS_BAR= '0' 
      else	   (others=>'Z');	
	RAM(conv_integer(ADR_IN)) <= Din when CS_BAR='0' and WR_BAR='0' else
					RAM(conv_integer(ADR_IN)) ;
end DATAFLOW;