ex_4_2_1_mux_cond.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
entity mux4_1 is
	Port(I0,I1,I2,I3,S0,S1:in std_logic;Y:out std_logic);
end mux4_1;
architecture DF_COND of mux4_1 is
begin
Y <=	 I0 after 5ns when (S1 & S0) = std_logic_vector'("00") else
	   I1 after 5ns when (S1 & S0) = std_logic_vector'("01") else
      I2 after 5ns when (S1 & S0) = std_logic_vector'("10") else
      I3 after 5ns when (S1 & S0) = std_logic_vector'("11") else
      'X';
end DF_COND;