ex_p4_18_hdlc_fsm.vhd

This is the course for VHDL programming

--FINITE STATE MACHINE TO DETECT 01111110 SEQUENCE
--Overlapping sequences are not allowed 
entity FSM_HDLCFLAG is
	port(RST,X,CLK :in BIT; Z: out BIT);
end FSM_HDLCFLAG;
architecture DF of FSM_HDLCFLAG is
	type STATE_TABLE is(RESET,GOT0,GOT01,GOT011,
	      GOT0111,GOT01111,GOT011111,GOT0111111);
	signal STATE,NEXT_STATE : STATE_TABLE;
begin
	process(CLK,RST,X)
	begin
	if(RST='1')then STATE <= RESET;
	elsif(CLK'event and CLK='1') then
		STATE<=NEXT_STATE;
	end if;
end process;
NEXT_STATE <= 
    RESET   	   when STATE=RESET        and X='1' else
	 GOT0    	   when STATE=RESET        and X='0' else
	 GOT01   	   when STATE=GOT0         and X='1' else
	 GOT0    	   when STATE=GOT0         and X='0' else
	 GOT011  	   when STATE=GOT01        and X='1' else
	 GOT0    	   when STATE=GOT01        and X='0' else
	 GOT0111 	   when STATE=GOT011       and X='1' else
	 GOT0    	   when STATE=GOT011       and X='0' else
	 GOT01111	   when STATE=GOT0111      and X='1' else
	 GOT0    	   when STATE=GOT0111      and X='0' else
	 GOT011111   when STATE=GOT01111     and X='1' else
	 GOT0    	   when STATE=GOT01111     and X='0' else
	 GOT0111111  when STATE=GOT011111    and X='1' else
	 GOT0    	   when STATE=GOT011111    and X='0' else
	 RESET ;
Z <= '1' when STATE= GOT0111111 and X='0' else	'0';
end DF;