ex_4_3_decoder.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER is
port(ADR : in  STD_LOGIC_VECTOR(2 downto 0);
	Y: out STD_LOGIC_VECTOR (7 downto 0));
End DECODER;
Architecture DF of DECODER is
Begin
	With ADR select
	Y<=	"00000001" when "000",
	"00000010" when "001",
	"00000100" when "010",
	"00001000" when "011",
	"00010000" when "100",
	"00100000" when "101",
	"01000000" when "110",
	"10000000" when "111",
	"XXXXXXXX" when others;
End DF;
Architecture BEH_IF of DECODER is
Begin
	process(ADR)
	begin
		if 	ADR="000" then Y <= "00000001";
		elsif	ADR="001" then Y <= "00000010";
		elsif	ADR="010" then Y <= "00000100";
		elsif	ADR="011" then Y <= "00001000";
		elsif	ADR="100" then Y <= "00010000";
		elsif	ADR="101" then Y <= "00100000";
		elsif	ADR="110" then Y <= "01000000";
		elsif	ADR="111" then Y <= "10000000";
		else		       Y <= "XXXXXXXX";
		end if;
	end process;
End BEH_IF;