ex_p4_25_mobius.vhd

This is the course for VHDL programming

--4 bit mobius counter
entity MOBIUS is
	port(CLK,RST:in BIT;COUNT:out BIT_VECTOR(3 downto 0));
end MOBIUS;
architecture a of  MOBIUS is
    signal IC: BIT_VECTOR(3 downto 0);
begin
	process(CLK,RST,IC)
	begin
		if RST = '1' then IC<="1111";
		elsif CLK = '1' and CLK'event then
			IC<= (IC(0) xor IC(1)) & IC(3 downto 1);
		end if;
	end process;
	COUNT <= IC;
end a;

entity TB_MOBIUS is	-- Test bench entity never has ports
end TB_MOBIUS;		-- It generates its own stimulus
architecture a of TB_MOBIUS is
	signal CLK,RST:bit;			--Give stimulus here
	signal COUNT:bit_vector(3 downto 0);--Observe this signal
begin
	M:entity work. MOBIUS 	-- Instantiate MOBIUS as M
		 port map(CLK, RST, COUNT);
	process
	begin
		RST <= '1'; wait for 10 ns; RST <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
		wait;
	end process;
end a;