ex_4_2_prio.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
entity PRI_ENC is
	port(I:in std_logic_vector(3 downto 0);
		   P:out std_logic_vector(1 downto 0);
		   A:out std_logic);
end PRI_ENC;
architecture COND_SEL of PRI_ENC is
begin
	A <= I(0) or I(1) or I(2) or I(3);	-- Active output
	P  <=	"11" when I(3) = '1' else	-- I(3) is highest priority
		"10" when I(2) = '1' else
		"01" when I(1) = '1' else
		"00" when I(0) = '1' else
		"00" when I(0) = '0' else
		"XX" ;
end COND_SEL;